Visible to Intel only — GUID: dvz1474788547368
Ixiasoft
1. Quick Start Guide
2. Detailed Description for Arria® 10 Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Arria® 10 Serial Lite III Streaming Advanced Clocking Mode
4. Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide
Visible to Intel only — GUID: dvz1474788547368
Ixiasoft
2.3.2. Reset Scheme
The mgmt_reset_n reset signal controls the overall reset structure for the design example. This is an asynchronous and active-low signal. Asserting this signal resets the demo control module and the Serial Lite III Streaming IP core. The traffic generator and traffic checker modules get reset through the demo management and the Serial Lite III Streaming IP core.
The following diagrams show the reset scheme implemented in the design examples.
Figure 9. Reset Scheme for Arria® 10 Serial Lite III Streaming Simplex Core in Standard Clocking Mode
Figure 10. Reset Scheme for Arria® 10 Serial Lite III Streaming Duplex Core in Standard Clocking Mode