Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide

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ID 683055
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Arria® 10 Serial Lite III Streaming Standard Clocking Mode 3. Detailed Description for Arria® 10 Serial Lite III Streaming Advanced Clocking Mode 4. Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Arria® 10 Serial Lite III Streaming Standard Clocking Mode x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. ATX PLL 2.3.1.3. Traffic Generator 2.3.1.4. Traffic Checker 2.3.1.5. Demo Control 2.3.1.6. Demo Management 2.3.1.7. Nios® V Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Arria® 10 Serial Lite III Streaming Advanced Clocking Mode x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. Source User Clock - I/O PLL 3.3.1.3. ATX PLL 3.3.1.4. Traffic Generator 3.3.1.5. Traffic Checker 3.3.1.6. Demo Control 3.3.1.7. Demo Management 3.3.1.8. Nios® V Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Arria® 10 Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Arria® 10 Serial Lite III Streaming Advanced Clocking Mode
4. Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide

5. Document Revision History for Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.05.23 24.1 19.3.0 Updated Nios II to Nios® V
2021.11.01 21.3 19.2.0
  • Renamed the document as Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide.
  • Rebranded the IP name Serial Lite III Streaming IP core to Serial Lite III Streaming Arria® 10 FPGA IP.
  • Removed mentions of NCSim support throughout the document:
  • Added support for QuestaSim* simulator.
  • Updated for latest branding standards.
2019.05.13 17.1 17.1
  • Clarified that hardware design examples are only supported in designs that generated from presets in Procedure and Presets topics. .
  • Rebranded SerialLite III Streaming IP core to Serial Lite III Streaming IP core.
Date Version Changes
November 2017 2017.11.06
  • Renamed the document as SerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices.
  • Added Knowledge Base link How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? inATX PLL chapter.
  • Updated for latest branding standards.
May 2017 2017.05.08
  • Rebranded as Intel.
  • Restructured document to migrate Stratix 10 device support to a new design example user guide.
  • Updated the Compiling and Testing the Design topic.
  • Updated the Directory and File Description for Design Example Folder table.
  • Updated the Testbench sub-topic for Detailed Description for Arria 10 SerialLite III Streaming Standard Clocking Mode chapter.
  • Updated the following figures:
    • Design Example for Simplex Core in Advanced Clocking Mode
    • Design Example for Duplex Core in Advanced Clocking Mode
    • Reset Scheme for Arria 10 SerialLite III Streaming Simplex Core in Advanced Clocking Mode
    • Reset Scheme for Arria 10 SerialLite III Streaming Duplex Core in Advanced Clocking Mode
    • Clocking Scheme for Arria 10 SerialLite III Streaming Simplex Core in Advanced Clocking Mode
    • Clocking Scheme for Arria 10 SerialLite III Streaming Duplex Core in Advanced Clocking Mode
  • Updated the Testbench sub-topic for Detailed Description for Arria 10 SerialLite III Streaming Advanced Clocking Mode chapter.
  • Minor typographical corrections.
December 2016 2016.12.09
  • Added 6x17.4Gbps presets for Stratix® 10Standard and Advanced Mode design examples.
  • Added error details list.
October 2016 2016.10.28
  • Added Stratix® 10 device support.
  • Restructured document.
May 2016 2016.05.02 Initial release.
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