Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide

ID 683055
Date 5/23/2024
Public
Document Table of Contents

5. Document Revision History for Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.05.23 24.1 19.3.0 Updated Nios II to Nios® V
2021.11.01 21.3 19.2.0
  • Renamed the document as Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide.
  • Rebranded the IP name Serial Lite III Streaming IP core to Serial Lite III Streaming Arria® 10 FPGA IP.
  • Removed mentions of NCSim support throughout the document:
  • Added support for QuestaSim* simulator.
  • Updated for latest branding standards.
2019.05.13 17.1 17.1
  • Clarified that hardware design examples are only supported in designs that generated from presets in Procedure and Presets topics. .
  • Rebranded SerialLite III Streaming IP core to Serial Lite III Streaming IP core.
Date Version Changes
November 2017 2017.11.06
  • Renamed the document as SerialLite III Streaming IP Core Design Example User Guide for Intel Arria 10 Devices.
  • Added Knowledge Base link How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? inATX PLL chapter.
  • Updated for latest branding standards.
May 2017 2017.05.08
  • Rebranded as Intel.
  • Restructured document to migrate Stratix 10 device support to a new design example user guide.
  • Updated the Compiling and Testing the Design topic.
  • Updated the Directory and File Description for Design Example Folder table.
  • Updated the Testbench sub-topic for Detailed Description for Arria 10 SerialLite III Streaming Standard Clocking Mode chapter.
  • Updated the following figures:
    • Design Example for Simplex Core in Advanced Clocking Mode
    • Design Example for Duplex Core in Advanced Clocking Mode
    • Reset Scheme for Arria 10 SerialLite III Streaming Simplex Core in Advanced Clocking Mode
    • Reset Scheme for Arria 10 SerialLite III Streaming Duplex Core in Advanced Clocking Mode
    • Clocking Scheme for Arria 10 SerialLite III Streaming Simplex Core in Advanced Clocking Mode
    • Clocking Scheme for Arria 10 SerialLite III Streaming Duplex Core in Advanced Clocking Mode
  • Updated the Testbench sub-topic for Detailed Description for Arria 10 SerialLite III Streaming Advanced Clocking Mode chapter.
  • Minor typographical corrections.
December 2016 2016.12.09
  • Added 6x17.4Gbps presets for Stratix® 10Standard and Advanced Mode design examples.
  • Added error details list.
October 2016 2016.10.28
  • Added Stratix® 10 device support.
  • Restructured document.
May 2016 2016.05.02 Initial release.