Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide

ID 683055
Date 5/23/2024
Public
Document Table of Contents

2.1. Features

Features for Standard Clocking Mode 2x10G design example includes:
  • Support 2 lanes with 10Gpbs transceiver data rate
  • Support simplex and duplex transmission modes
  • Traffic checker for data verification and lane de-skew verification
  • Support CRC error injection using Nios® V processor
Features for Standard Clocking Mode 6x12.5G design example includes:
  • Support 6 lanes with 12.5Gpbs transceiver data rate
  • Support simplex and duplex transmission modes
  • Traffic checker for data verification and lane de-skew verification
  • Support CRC error injection using Nios® V processor