Serial Lite III Streaming Arria® 10 FPGA IP Design Example User Guide

ID 683055
Date 5/23/2024
Public
Document Table of Contents

1.3.3. Presets

Standard presets allow instant entry of pre-selected parameter values in the IP and Example Design tabs. You can select the presets at the lower right window in the parameter editor.

The parameter values chosen for the presets belong to the group of supported Serial Lite III Streaming IP configurations for design example generation. You can select one of the presets available for your target device to quickly generate a design example without having to manually set each parameter in the IP tab and verifying that the parameter matches the supported configurations set.

Note: Only designs generated from the presets support hardware design examples.

There are four preset settings available in the library that support Duplex, Sink and Source modes:

  • Advanced Clocking Mode 2x10G
  • Advanced Clocking Mode 6x12.5G
  • Standard Clocking Mode 2x10G
  • Standard Clocking Mode 6x12.5G
Table 3.  Parameter Settings for Arria® 10 Design Example Presets
Presets Advanced Clocking Mode 2x10G Advanced Clocking Mode 6x12.5G Standard Clocking Mode 2x10G Standard Clocking Mode 6x12.5G
Direction Duplex, Sink, and Source Duplex, Sink, and Source Duplex, Sink, and Source Duplex, Sink, and Source
Number of lanes 2 6 2 6
Meta frame length in words 200 8191 200 8191
Transceiver reference clock frequency (MHz) 644.53125 312.5 644.531187 312.5
Enable M20K ECC support ON and OFF ON and OFF ON and OFF ON and OFF
Clocking Mode Advanced clocking mode Advanced clocking mode Standard clocking mode Standard clocking mode
Required user clock frequency (MHz) 150.8395522

186.4760558

146.484375 177.556818
Transceiver data rate (Gbps) 10.3125 12.5 10.312499 12.5