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2.1. Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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3.4.3.1.3. hdcp2x_rx_kmem.v file
For hdcp2x_rx_kmem.v file
- To identify the correct HDCP2 RX DCP key file for hdcp2x_rx_kmem.v, make sure the first 4 bytes of the file are “0x00, 0x00, 0x00, 0x02”.
- The keys in the DCP key files are in little-endian format.
Figure 22. Byte Mapping from HDCP2 RX DCP Key File into hdcp2x_rx_kmem.v
The following figure shows the exact byte mapping from HDCP2 RX DCP key file into hdcp2x_rx_kmem.v
Note: The byte number displays in the following format:
- Key size in bytes * key number + byte number in current row + constant offset + row size in bytes * row number.
- 862*n indicates that each key set has 862 bytes.
- 16*y indicates that each row has 16 bytes. There is an exception in cert_rx_prod where ROW 32 has only 10 bytes.
Figure 23. HDCP2 RX DCP Key File Filling with Junk Values
Figure 24. Wire Arrays of hdcp2x_rx_kmem.v
The following figure shows the wire arrays for hdcp2x_rx_kmem.v (cert_rx_prod, kprivrx_qinv_prod, and lc128_prod) map to the example of HDCP2 RX DCP key file in Figure 23.