DisplayPort Arria® 10 FPGA IP Design Example User Guide

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ID 683050
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Design Examples 3. HDCP Over DisplayPort Design Example 4. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. DisplayPort Intel® FPGA IP Design Example Hardware and Software Requirements 1.3. Generating the DisplayPort Intel® FPGA IP Design Example 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating .elf File
2. DisplayPort Design Examples x
2.1. Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features x
2.4.1. Arria® 10 DisplayPort SST TX-only Design Features 2.4.2. Arria® 10 DisplayPort SST RX-only Design Features
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® V Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Setting Up the Hardware 3.4.2. Generating the Design 3.4.3. Including HDCP Production Keys 3.4.4. Compiling the Design 3.4.5. Viewing the Results
3.4.3. Including HDCP Production Keys x
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example
4. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Arria® 10 FPGA IP Design Example User Guide

2.11. Transceiver Lane Configurations

If you want to configure your design to use 1, 2 or 4 lanes targeting different versions of Bitec FMC daughter cards, you have to configure the pin assignments accordingly in the Quartus® Prime Pro Settings File (QSF).
To configure the DisplayPort Intel® FPGA IP design example using 1, 2 or 4 lanes, follow these steps:
  1. In both the DisplayPort Source and Sink parameter editors, set the Maximum lane count parameter to 1, 2 or 4.
  2. Generate the design example.
  3. Make the following assignments in the Assignment Editor.
    Table 23.  Pin Assignments for Bitec FMC Revision 8 or Earlier
    DisplayPort Pin Location

    ( Arria® 10 Development Kit)

    		Four Lanes Two Lanes One Lane
    Source BC7 fmca_dp_c2m_p[0] Not applicable Not applicable
    BC8 fmca_dp_c2m_n[0]
    BD5 fmca_dp_c2m_p[1]
    BD6 fmca_dp_c2m_n[1]
    BB5 fmca_dp_c2m_p[2] fmca_dp_c2m_p[0]
    BB6 fmca_dp_c2m_n[2] fmca_dp_c2m_n[0]
    BC3 fmca_dp_c2m_p[3] fmca_dp_c2m_p[1] fmca_dp_c2m_p[0]
    BC4 fmca_dp_c2m_n[3] fmca_dp_c2m_n[1] fmca_dp_c2m_n[0]
    Sink AW7 fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] fmca_dp_m2c_p[0]
    AW8 fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] fmca_dp_m2c_n[0]
    BA7 fmca_dp_m2c_p[1] fmca_dp_m2c_p[1] Not applicable
    BA8 fmca_dp_m2c_n[1] fmca_dp_m2c_n[1]
    AY5 fmca_dp_m2c_p[2] Not applicable
    AY6 fmca_dp_m2c_n[2]
    AV5 fmca_dp_m2c_p[3]
    AV6 fmca_dp_m2c_n[3]
    Transceiver Avalon® Memory-Mapped Interface Group XCVR_RECONFIG_GROUP Enable Disable Disable
    Table 24.  Pin Assignments for Bitec FMC Revision 10
    DisplayPort Pin Location ( Arria® 10 Development Kit) Four Lanes Two Lanes One lane
    Source BC7 fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] fmca_dp_c2m_p[0]
    BC8 fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] fmca_dp_c2m_n[0]
    BD5 fmca_dp_c2m_p[1] fmca_dp_c2m_p[1] Not Applicable
    BD6 fmca_dp_c2m_n[1] fmca_dp_c2m_n[1]
    BB5 fmca_dp_c2m_p[2] Not Applicable
    BB6 fmca_dp_c2m_n[2]
    BC3 fmca_dp_c2m_p[3]
    BC4 fmca_dp_c2m_n[3]
    Sink AW7 fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] fmca_dp_m2c_p[0]
    AW8 fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] fmca_dp_m2c_n[0]
    BA7 fmca_dp_m2c_p[1] fmca_dp_m2c_p[1] Not Applicable
    BA8 fmca_dp_m2c_n[1] fmca_dp_m2c_n[1]
    AY5 fmca_dp_m2c_p[2] Not Applicable
    AY6 fmca_dp_m2c_n[2]
    AV5 fmca_dp_m2c_p[3]
    AV6 fmca_dp_m2c_n[3]
    Merging of Reconfiguration Interfaces XCVR_RECONFIG_GROUP Enable Enable Enable
    Table 25.  Pin Assignments for Bitec FMC Revision 11
    DisplayPort Pin Location

    ( Arria® 10 Development Kit)

    		Four Lanes Two Lanes One Lane
    Source BC7 fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] fmca_dp_c2m_p[0]
    BC8 fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] fmca_dp_c2m_n[0]
    BD5 fmca_dp_c2m_p[1] fmca_dp_c2m_p[1] Not applicable
    BD6 fmca_dp_c2m_n[1] fmca_dp_c2m_n[1]
    BB5 fmca_dp_c2m_p[2] Not applicable
    BB6 fmca_dp_c2m_n[2]
    BC3 fmca_dp_c2m_p[3]
    BC4 fmca_dp_c2m_n[3]
    Sink AW7 fmca_dp_m2c_p[0] Not applicable Not applicable
    AW8 fmca_dp_m2c_n[0]
    BA7 fmca_dp_m2c_p[1]
    BA8 fmca_dp_m2c_n[1]
    AY5 fmca_dp_m2c_p[2] fmca_dp_m2c_p[0]
    AY6 fmca_dp_m2c_n[2] fmca_dp_m2c_n[0]
    AV5 fmca_dp_m2c_p[3] fmca_dp_m2c_p[1] fmca_dp_m2c_p[0]
    AV6 fmca_dp_m2c_n[3] fmca_dp_m2c_n[1] fmca_dp_m2c_n[0]
    Transceiver Avalon® Memory-Mapped Interface Group XCVR_RECONFIG_GROUP Enable Disable Disable
    Note: You can disable the non-applicable pin assignments in the Assignment Editor.
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