DisplayPort Arria® 10 FPGA IP Design Example User Guide

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ID 683050
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Design Examples 3. HDCP Over DisplayPort Design Example 4. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. DisplayPort Intel® FPGA IP Design Example Hardware and Software Requirements 1.3. Generating the DisplayPort Intel® FPGA IP Design Example 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating .elf File
2. DisplayPort Design Examples x
2.1. Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features x
2.4.1. Arria® 10 DisplayPort SST TX-only Design Features 2.4.2. Arria® 10 DisplayPort SST RX-only Design Features
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® V Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Setting Up the Hardware 3.4.2. Generating the Design 3.4.3. Including HDCP Production Keys 3.4.4. Compiling the Design 3.4.5. Viewing the Results
3.4.3. Including HDCP Production Keys x
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example
4. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Arria® 10 FPGA IP Design Example User Guide

3.4.2. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in the Quartus® Prime Pro Edition software to generate the design example.
Before you begin, ensure to install the HDCP feature in the Quartus® Prime Pro Edition software.
  1. Click Tools > IP Catalog, and select Arria® 10 as the target device family.
    Note: The HDCP design example supports Stratix® 10, Arria® 10, and Agilex™ 7 devices.
  2. In the IP Catalog, locate and double-click DisplayPort Intel® FPGA IP . The New IP variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.qsys.
  4. You may select a specific device in the Device field, or keep the default software device selection.
  5. Click OK. The parameter editor appears.
  6. Configure the desired parameters for both TX and RX
    Note: To enable the HDCP feature on RX, turn on the Enable GPU Mode parameter.
  7. Turn on Support HDCP Key Management parameter if you want to store the HDCP production key in an encrypted format in the external flash memory or EEPROM. Otherwise, turn off this parameter to store the HDCP production key in plain format in the FPGA.
  8. On the Design Example tab, select DisplayPort SST Parallel Loopback With PCR .
  9. Select Synthesis to generate the hardware design example.
  10. For Target Development Kit, select Arria 10 GX FPGA Development Kit . This causes the target device selected in step 4 to change to match the device on the development kit. For Arria 10 GX FPGA Development Kit, the default device is 10AX115S2F45I1SG.
  11. Click Generate Example Design to generate the project files and the software Executable and Linking Format (ELF) programming file.
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