2024.04.29 |
24.1 |
20.0.0 |
- Updated mentions of Nios® II to Nios® V (where applicable).
- Changed the document title from DisplayPort Intel Arria 10 FPGA IP Design Example User Guide to DisplayPort Arria 10 FPGA IP Design Example User Guide.
- Added a note about obtaining Nios® V evaluation license in the Generating the Design topic.
- Added Windows WSL1 and Ubuntu to software requirements
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2023.02.01 |
21.4 |
20.0.0 |
Made corrections to Table 11 (DisplayPort RX PHY Top and TX PHY Top Components) in the Design Components topic related supported data rate. |
2021.12.13 |
21.4 |
20.0.0 |
- Added DisplayPort SST TX-only and DisplayPort SST RX-only to DisplayPort Intel FPGA IP Design Example Quick Start Guide topic.
- Added DisplayPort SST TX-only and DisplayPort SST RX-only design examples in DisplayPort Intel FPGA IP Design Example Parameters topic.
- Renamed Parallel Loopback Design Examples topic to DisplayPort Design Examples.
- Added DisplayPort SST TX-only and DisplayPort SST RX-only information in DisplayPort Intel FPGA IP Design Example for Intel Arria 10 Devices table.
- Added a new chapter Intel Arria 10 DisplayPort SST TX-only or RX-only Design Features.
- Added Test Pattern Generator II (TX-only design) and Clocked Video Output II (TX-only design) to Design Components topic.
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2021.11.12 |
21.3 |
19.4.0 |
- Replaced AN556 to AN556: Using the DesignSecurity Features in Intel FPGAs in Protection of Encryption Key Embedded in FPGA Design.
- Updated the subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) to describe the new key encryption software utility (KEYENC).
- Removed the following figures:
- Data array of Facsimile Key R1 for RX Private Key
- Data arrays of HDCP Production Keys (Placeholder)
- Data array of HDCP Protection Key (Predefined key)
- HDCP protection key initialized in hdcp2x_tx_kmem.mif
- HDCP protection key initialized in hdcp1x_rx_kmem.mif
- HDCP protection key initialized in hdcp1x_tx_kmem.mif
- Moved subsection HDCP Key Mapping from DCP Key Files from Debug Guidelines to Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0).
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2021.09.15 |
21.1 |
19.4.0 |
Removed referenes to ncsim |
2021.05.11 |
21.1 |
19.4.0 |
- Added SUPPORT HDCP KEY MANAGEMENT = 1 to the description for Figure : HDCP Over DisplayPort Design Example Block Diagram.
- Added the steps in HDCP over DisplayPort design example in Design Walkthrough.
- Added the step to turn on Support HDCP Key Management parameter in Generate the Design.
- Added a new subsection Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1).
- Added a new chapter Protection of Encryption Key Embedded in FPGA Design.
- Added a new chapter Debug Guidelines and subsection HDCP Status Signals, Modifying HDCP Software Parameter, and Frequently Asked Questions.
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2020.09.28 |
20.3 |
19.4.0 |
- Updated and renamed the Configuring Single or Dual Lanes section to Transceiver Lane Configurations.
- Added pin assignments for Bitec FMC revision 10 in the Transceiver Lane Configurations section.
- Updated the pin assignments for Bitec FMC revision 8 or earlier, and revision 11 with transceiver Avalon® memory-mapped interface group information in the Transceiver Lane Configurations section.
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2020.04.13 |
20.1 |
19.3.0 |
- Updated the Bitec DisplayPort card revision and the IP version in the local parameter in the RTL file at <project directory>/rtl/a10_dp_demo.v and the software config.h file in the Compiling and Testing the Design section.
- Updated the description for the fmca_la_tx_n_12 signal and added a new signal, fmca_la_tx_p_14 for DisplayPort FMC daughter card pins in the Interface Signals and Parameters section for DisplayPort loopback design examples.
- Replaced the description about the Parade Tech PS8460 Retimer signals with the FMC On-board Retimer Reconfiguration Interface signals in the Interface Signals and Parameters section for DisplayPort loopback design examples.
- Added information about the HDCP design example in the HDCP Over DisplayPort Design Examples section. This information is removed from the DisplayPort Intel® FPGA IP User Guide.
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2019.07.30 |
19.2 |
19.1.0 |
- Added information about the DisplayPort MST parallel loopback with and without a PCR module design examples in the DisplayPort Intel® FPGA IP Design Example Quick Start Guide section.
- Updated the files and folders in the Directory Structure section.
- Added support for the Bitec DisplayPort FMC daughter card revision 11 in the Hardware and Software Requirements section.
- Added information about the DisplayPort MST parallel loopback with and without a PCR module design examples in the Generating the Design, DisplayPort Intel® FPGA IP Design Example Parameters, and DisplayPort Intel® FPGA IP Design Example Detailed Description sections.
- Updated the Regenerating ELF File section to include information about WSL and provided a link to the Nios II Software Developer Handbook.
- Updated the Compiling and Testing the Design section to include information about the Bitec DisplayPort FMC daughter card revision 11 and channel mapping.
- Updated the Configuring Single or Dual Lanes section with information about the Bitec DisplayPort FMC daughter card revision 11.
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2019.04.05 |
19.1 |
19.1 |
- Renamed Intel FPGA DisplayPort to DisplayPort Intel® FPGA IP .
- Updated the Directory Structure section to add the Xcelium* Parallel simulator files.
- Added instructions to run simulation using the Xcelium* Parallel simulator in the Simulation the Design section.
- Edited the DisplayPort Design Example Supported EDA Simulators table in the Simulation Testbench section to include Xcelium* Parallel simulator and the supported platforms.
- Removed the /altera_avalon_i2c file from the Directory Structure section. It is not added in the core folder.
- Moved the .c and .h software files to a new folder in the Directory Structure section. These files are now in the dp_demo subfolder in version 19.1 of the DisplayPort Intel® FPGA IP .
- Updated the Bitec DisplayPort FMC daughter card local parameter in the Compiling and Testing the Design section.
- Edited the note about CRC calculation in the Simulation Testbench section. To ensure CRC is calculated, you must enable the Support CTS test automation parameter.
- Updated the frequency rate for HBR quad symbols per clock to 67.5 for the RX and TX Transceiver Clockout descriptions in the Clocking Scheme section.
- Added the Arria® 10 DisplayPort SST Parallel Loopback with Adaptive Sync Support section to provide guidelines to add the Adaptive Sync feature,
- Added the Configuring Single or Dual Lanes section to provide guidelines to make the correct pin assignments for single and dual lanes.
- Added a link to AN 883: Intel Arria 10 DisplayPort TX-only Design in the Creating RX-only or TX-only Designs section. This application note provides information about how to create TX-only designs to transmit 4Kp60 video output generated by the Test Pattern Generator II Intel FPGA IP.
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