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2.1. Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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Ixiasoft
1.6. DisplayPort Intel® FPGA IP Design Example Parameters
Parameter | Value | Description |
---|---|---|
Available Design Example | ||
Select Design |
|
Select the design example to be generated.
Note: Only DisplayPort SST Parallel Loopback with PCR is available in the Quartus® Prime Standard Edition.
|
Design Example Files | ||
Simulation | On, Off | Turn on this option to generate the necessary files for the simulation testbench. |
Synthesis | On, Off | Turn on this option to generate the necessary files for Quartus® Prime compilation and hardware demonstration. |
Generated HDL Format | ||
Generate File Format | Verilog, VHDL | Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
|
Target Development Kit | ||
Select Board |
|
Select the board for the targeted design example.
|
Target Device | ||
Change Target Device | On, Off | Turn on this option and select the preferred device variant for the development kit. |