DisplayPort Arria® 10 FPGA IP Design Example User Guide

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ID 683050
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Design Examples 3. HDCP Over DisplayPort Design Example 4. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. DisplayPort Intel® FPGA IP Design Example Hardware and Software Requirements 1.3. Generating the DisplayPort Intel® FPGA IP Design Example 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating .elf File
2. DisplayPort Design Examples x
2.1. Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features x
2.4.1. Arria® 10 DisplayPort SST TX-only Design Features 2.4.2. Arria® 10 DisplayPort SST RX-only Design Features
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® V Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Setting Up the Hardware 3.4.2. Generating the Design 3.4.3. Including HDCP Production Keys 3.4.4. Compiling the Design 3.4.5. Viewing the Results
3.4.3. Including HDCP Production Keys x
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Design Examples
3. HDCP Over DisplayPort Design Example
4. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Arria® 10 FPGA IP Design Example User Guide

3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files

For hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files
  • These two files are sharing the same format
  • To identify the correct HDCP1 TX DCP key file for hdcp1x_tx_kmem.v, make sure the first 4 bytes of the file are “0x01, 0x00, 0x00, 0x00”.
  • To identify the correct HDCP1 RX DCP key file for hdcp1x_rx_kmem.v, make sure the first 4 bytes of the file are “0x02, 0x00, 0x00, 0x00”.
  • The keys in the DCP key files are in little-endian format. To use in kmem files, you must convert them into big-endian.
Figure 19. Byte Mapping from HDCP1 TX DCP Key File into hdcp1x_tx_kmem.v

The following figure shows the exact byte mapping from HDCP1 TX DCP key file into hdcp1x_tx_kmem.v. The same mapping applies to hdcp1x_rx_kmem.v.

Note: The byte number displays in below format:
  • Key size in bytes * key number + byte number in current row + constant offset + row size in bytes * row number
  • 308*n indicates that each key set has 308 bytes.
  • 7*y indicates that each row has 7 bytes.
Figure 20. HDCP1 TX DCP Key File Filling with Junk Values
Figure 21. Wire Arrays of hdcp1x_tx_kmem.v

The following figure shows an example of hdcp1x_tx_kmem.v and how its wire arrays map to the example of HDCP1 TX DCP key file in Figure 20.

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