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2.1. Arria® 10 DisplayPort SST Parallel Loopback Design Features
2.2. Arria® 10 DisplayPort MST Parallel Loopback Design Features
2.3. Enabling Adaptive Sync Support
2.4. Arria® 10 DisplayPort SST TX-only or RX-only Design Features
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameters
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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3.4.5. Viewing the Results
At the end of the demonstration, you will be able to view the results on the HDCP-enabled DisplayPort external sink.
To view the results of the demonstration, follow these steps:
- Power up the Intel FPGA board.
- Change the directory to <project directory>/quartus/ directory.
- Type the following command on the Nios® V Command Shell to download the Software Object File (.sof) to the FPGA.
quartus_pgm -m jtag -o p;<Intel Quartus Prime project name>.sof.
- Power up the HDCP-enabled DisplayPort external source and sink (if you have not done so). The DisplayPort external sink displays the output of your DisplayPort external source.