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1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
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Ixiasoft
7.5. Status Interface
Signal | Direction | Description |
---|---|---|
led_link block_lock rx_block_lock |
Out | Asserted when the link synchronization is successful. |
led_an ethernet_1g_an |
Out | Asserted when auto-negotiation is completed. |
led_char_err ethernet_1g_char_err |
Out | Asserted when a 10-bit character error is detected in the RX data. |
led_disp_err ethernet_1g_disp_err |
Out | Asserted when a 10-bit running disparity error is detected in the RX data. |
channel_ready channel_tx_ready channel_rx_ready tx_ready_export rx_ready_export |
Out | Asserted when the channel is ready for data transmission. |
atx_pll_locked | Out | Asserted when the TX PLL is locked. |
xgmii_rx_link_fault_status | Out | This signal indicates the status of the received data bytes. High indicates fault data bytes. |
tod_sampling_pll_locked | Out | This signal indicates the lock status of TOD Synchronizer sampling clock PLL. |
dl_sampling_pll_locked | Out | This signal indicates the lock status of deterministic latency measurement sampling clock PLL. |