Visible to Intel only — GUID: nfa1462536093312
Ixiasoft
1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
Visible to Intel only — GUID: nfa1462536093312
Ixiasoft
6.3.1. Design Components
Component | Description |
---|---|
LL 10GbE MAC | The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
|
PHY | The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
|
Channel address decoder | Decodes the addresses of the components in each Ethernet channel, such as PHY and LL 10GbE MAC. |
Multi-channel address decoder | Decodes the addresses of the components used by all channels , such as the Master ToD module. |
Top address decoder | Decodes the addresses of the top-level components, such as the Traffic Controller. |
Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP. Resets the transceiver. |
ATX PLL | Generates a TX serial clock for the Intel® Stratix® 10 transceiver. |
Core fPLL | Generates clocks for all design components. |
Design Components for the IEEE 1588v2 Feature | |
ToD Sampling fPLL | Generates the clocks for the 1588 design components. |
Master TOD | The master TOD for all channels. |
TOD Synch | Synchronizes the master TOD to all local TODs. |
Local TOD | The TOD for each channel. |
Master PPS | The master PPS. Returns pulse per second (pps) for all channels. |
PPS | The slave PPS. Returns pulse per second (pps) for each channel. |
PTP Packet Classifier | Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel® FPGA IP. |