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1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
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4.5.1. Test Procedure
Follow these steps to test the design examples in hardware:
- Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>
Example: TEST_EXT_LB 0 2.5G 1000000000
Table 11. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 1G, 2.5G The PHY speed. burst_size An integer value The number of packets to generate for the test. - When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the Ethernet packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters.
Figure 24. Sample Test Output—Ethernet Packet MonitorFigure 25. Sample Test Output—Statistics Counters