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1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
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3.3.1. Design Components
Component | Description |
---|---|
LL 10GbE MAC | The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
|
PHY | The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
|
Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® FPGA IP. Resets the transceiver. |
Address Decoder | Decodes the addresses of the components. |
Avalon® Memory-Mapped Mux Transceiver Reconfig | Provides the transceiver reconfig block and system console access to the Avalon® memory-mapped interface of the PHY. |
Transceiver Reconfig | Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa. |
ATX PLL | Generates a TX serial clock for the Intel® Stratix® 10 2.5G and 10G transceiver. |
fPLL | Generates a TX serial clock for the Intel® Stratix® 10 1G transceiver. |
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