2024.01.08 |
23.4 |
22.0.4 |
Updated frequency settings in Hardware Testing topic for 10M/100M/1G/2.5G/10G Ethernet Design Example. |
2023.12.14 |
23.3 |
22.0.3 |
- Updated frequency settings in Hardware Testing topic for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example.
- Updated frequency settings in Hardware Testing topic for 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature.
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2023.10.02 |
23.3 |
22.0.3 |
Updated QSFP28 IF1 frequency settings in Hardware Testing topic for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature. |
2023.04.10 |
23.1 |
19.3.0 |
Updated Hardware and Software Requirements topic and Hardware Testing topic for the following design example:
- 10GBASE-R Ethernet Design Example
- 10M/100M/1G/2.5G/10G Ethernet Design Example
- 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
|
2023.02.16 |
21.2 |
19.3.0 |
Updated Hardware Testing topic for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature. |
2022.01.11 |
21.2 |
19.3.0 |
Updated Figure: Clocking Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example to correct input and output clock for PLL. |
2021.10.22 |
21.2 |
19.3.0 |
- Updated reference to target device 1SX280HU1F50E2VG to 1SG280HU1F50E2VG.
- Updated the description and steps to Changing Target Device in Hardware Design Example and Procedure in the Quick Start Guide chapter.
- Removed references to NCSim simulator throughout the document.
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2020.11.30 |
19.3 |
19.3.0 |
Updated the 10GBASE-R Ethernet Design Example chapter:
- Updated Figure: Clocking and Reset Scheme for 10GBASE-R Design Example
- Updated Figure: Interface Signals of the 10GBASE-R Ethernet Design Example
- Updated for latest branding standards.
|
2020.09.28 |
19.3 |
19.3.0 |
Updated the 10GBASE-R Ethernet Design Example chapter:
- Added new topics:
- Configuring FIFO Depth for Avalon® Streaming Loopback.
- Running Avalon® Streaming Loopback Test Case with Jumbo Ethernet Packets.
- Updated the description for FIFO in Table: Design Components in the 10GBASE-R Ethernet Design Example chapter.
- Made editorial edits throughout the document.
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2020.06.30 |
19.3 |
19.3.0 |
Updated Figure: Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example With IEEE 1588v2 Feature to correct the frequency values for latency_sclk, TOD clk_sampling, and tx_serial_clk. |
2019.12.13 |
19.3 |
19.3.0 |
- Added a note to the procedure steps in the Compiling and Simulating the Design section.
- Added a new Topic—Updating PHY IP Design File Names.
- Updated the procedure steps in the Changing Target Device in Hardware Design Example section.
- Updated for latest Intel® branding standards.
|
2019.10.02 |
19.3 |
19.3.0 |
- Added new topic—Changing Target Device in Hardware Design Example.
- Updated references to Intel® Stratix® 10 GX Signal Integrity H-Tile (ES) Development Kit as Intel® Stratix® 10 GX Signal Integrity H-Tile (Production) Development Kit.
- Updated the Generating the Design topic to add a note to Step 8.
- Updated Figure: Example Design Tab.
- Updated the Hardware and Software Requirements topics for all design example chapters
- Updated Table: 1G/2.5G/5G/10G Multi-rate PHY Register Definitions.
|
2019.07.01 |
19.2 |
19.2.0 |
- Updated all references to Stratix 10 H-Tile GX Transceiver Signal Integrity Development Kit to Stratix 10 GX Signal Integrity H-Tile (ES) Development Kit.
- Updated Table: Parameters in the Example Design Tab:
- Updated the parameter name Example Design Files for Simulation or Synthesis to Example Design Files.
- Updated the parameter name Enable NPDME support to Enable Native PHY Debug Master Endpoint (NPDME).
- Updated Figure: Example Design Tab.
- Updated Table: Design Components of the 10GBASE-R Ethernet design example to update the description for FIFO.
- Made editorial edits through out the document.
|
2019.04.30 |
19.1 |
19.1 |
- Updated Table: Parameters in the Example Design Tab to update the description for Select Board.
- Updated Figure: Block Diagram of the Hardware Setup.
- Updated the hardware requirements in the Hardware and Software Requirements topics for all design examples.
|
2019.04.24 |
19.1 |
19.1 |
- Changed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
|
2018.09.24 |
18.0 |
18.0 |
- Updated Table: Parameters in the Example Design Tab to include a note to parameters Enable NPDME support and Analog Voltage to clarify that these options are only available from Intel Quartus Prime Pro Edition version 17.0 onwards.
- Removed Debug Signals topic from the 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices chapter.
- Updated the Configuration Registers Description chapter:
- Added the following topics:
- Register Access Definition
- 1G/2.5G/5G/10G PHY
- Removed the Register Map topic.
- Added Timing Constraints topic to the following design example chapters:
- 10M/100M/1G/2.5G/10G Ethernet Design for Intel Stratix 10 Devices
- 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices
- 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices
|
2018.08.08 |
18.0 |
18.0 |
- Updated Table: Hardware Test Cases of the 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices chapter to update the description for source gen_conf.tcl command of the SFP+ loopback test case.
- Updated Figure: Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example.
- Updated Table: Avalon-MM Interface Signals:
- Added the following signals:
- csr_mch_write
- csr_mch_writedata
- csr_mch_read
- csr_mch_readdata
- csr_mch_address
- csr_mch_waitrequest
- Removed the following signals:
- csr_write
- csr_writedata
- csr_read
- csr_readdata
- csr_address
- csr_waitrequest
|
2018.05.16 |
18.0 |
18.0 |
- Updated for latest branding standards.
- Made editorial text updates throughout the document.
- Added support for Xcelium simulator.
- Renamed the document as Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IP Design Example User Guide.
- Updated the procedure steps of the Compiling and Testing the Design in Hardware topic.
- Updated the Test Cases topic of the 10BASE-R Ethernet Design Example for Intel Stratix 10 Devices chapter.
- Updated the 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices chapter:
- Updated all references to 10G USXGMII references to 10M/100M/1G/2.5G/5G/10G (USXGMII).
- Added 1588v2 feature support to the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet design example chapter.
- Added new Simulation topics:
- Test Case—Design Example with the IEEE 1588v2 Feature
- Test Case—Design Example without the IEEE 1588v2 Feature
- Updated Table: Command Parameters.
- Updated Table: Register Map to include byte offset for Native PHY Reconfiguration block.
- Updated the Test Procedure topic of the 10M/100M/1G/2.5G Ethernet Design Example for Intel Stratix 10 Devices chapter.
- Updated the Hardware and Software Requirements, Design Components, and Hardware Testing topics for all design example chapters.
- Updated the following Tables:
- Directory and File Description
- Parameters in the Example Design Tab
- Clock and Reset Interface Signals
- Updated the following Figures:
- Block Diagram—10GBASE-R Ethernet Design Example
- Clocking and Reset Scheme for 10GBASE-R Design Example
- Reset Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example
- Block Diagram—1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
- Block Diagram—1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
- Reset Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
- Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example Without IEEE 1588v2 Feature
- Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
|
2018.03.28 |
17.1 |
17.1 |
- Updated Figure: Clocking Scheme for 10G USXGMII Ethernet Design Example.
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