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1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
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8.4. Transceiver Reconfiguration
Word Offset | Name | Bits | Description | Access | HW Reset |
---|---|---|---|---|---|
0x00 | logical_channel_number | [9:0] | The logical number of the reconfiguration block. | RW | 0x000 |
[31:10] | Reserved | ||||
0x01 | control | [1:0] | Specify the new operating speed:
|
RW | 0x00 |
[15:2] | Reserved | — | 0x000 | ||
[16] | Writing 1 to this bit when it is 0 starts the reconfiguration process. The bit clears when the process is completed. |
RWC | 0x0 | ||
[31:17] | Reserved | — | 0x000000 | ||
0x02 | status | [0] | When set to 1, indicates the reconfiguration process is in progress. | RO | 0x0 |
[31:1] | Reserved | — | — |