Visible to Intel only — GUID: fav1502333658669
Ixiasoft
1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
Visible to Intel only — GUID: fav1502333658669
Ixiasoft
5.5. Hardware Testing
Follow the procedure at the provided link to test the design example in the selected hardware.
The design example is using QSFP28 IF1 by default. To use SFP+, follow instruction in Changing to SFP+ Setting.
In the Clock Controller application, which is part of the development kit, set the following frequencies:
For QSFP28 IF1 setting:
- U5, OUT 5—644.53125 MHz
- U5, OUT 0—125 MHz
- U6, OUT 8—125 MHz
For SFP+ setting:
- Y1—644.53125 MHz
- U5, OUT 1—125 MHz
- U5, OUT 8—125 MHz