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1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example
3. 10M/100M/1G/2.5G/10G Ethernet Design Example
4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature
5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature
6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
7. Interface Signals Description
8. Configuration Registers Description
9. Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
10. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Stratix® 10 FPGA IP Design Example User Guide
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4.3.1. Design Components
Component | Description |
---|---|
LL 10GbE MAC | The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
|
PHY | The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
|
Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP. Resets the transceiver. |
Avalon® Memory-Mapped Mux Transceiver Reconfig | Provides the transceiver reconfig block and system console access to the PHY's Avalon® memory-mapped interface. |
Transceiver Reconfig | Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa. |
ATX PLL | Generates a TX serial clock for the Intel® Stratix® 10 2.5G transceiver. |
fPLL | Generates a TX serial clock for the Intel® Stratix® 10 1G transceiver. |
Core fPLL | Generates 156.25 MHz clocks to MAC IP, reset synchronizer, Ethernet traffic controller, PTP packet classifier, and address decoder. |
Design Components for the IEEE 1588v2 Feature | |
IO PLL | Generates the clocks for the 1588 design components. |
Master Time-of-Day (TOD) | The master TOD for all channels. |
TOD Synch | Synchronizes the master TOD to all local TODs. |
Local TOD | The TOD for each channel. |
Master Pulse Per Second (PPS) | The master PPS. Returns pulse per second (pps) for all channels. |
PPS | The slave PPS. Returns pulse per second (pps) for each channel. |
PTP Packet Classifier | Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel® FPGA IP. |
Related Information