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1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History
4.4.1. Features
4.4.2. PTP Timestamp Accuracy
4.4.3. PTP Client Flow
4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants
4.4.5. Virtual Lane Order and Offset Values
4.4.6. UI Adjustment
4.4.7. Reference Time Interval
4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
4.4.9. UI Value and PMA Delay
4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
5.1. Clock Connections in Single Instance Operation
5.2. Clock Connections in Multiple Instance Operation
5.3. Clock Connections in MAC Asynchronous FIFO Operation
5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation
5.5. Clock Connections in Synchronous Ethernet Operation
5.6. Custom Cadence
7.1. Status Interface
7.2. TX MAC Avalon ST Client Interface
7.3. RX MAC Avalon ST Aligned Client Interface
7.4. TX MAC Segmented Client Interface
7.5. RX MAC Segmented Client Interface
7.6. MAC Flow Control Interface
7.7. PCS Mode TX Interface
7.8. PCS Mode RX Interface
7.9. FlexE and OTN Mode TX Interface
7.10. FlexE and OTN Mode RX Interface
7.11. Custom Rate Interface
7.12. Reconfiguration Interfaces
7.13. Precision Time Protocol Interface
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough
7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough
7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion
7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough
7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough
7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion
7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
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7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough
Figure 29. Fields and Frame Boundaries in an Ethernet PacketWhen you turn off Preamble Passthrough in the parameter editor, i_tx_data must be written as shown below for the first cycle of data presented to the MAC.
Note: For 10GE/25GE channels, multiple cycles are required to write the header data.
100GE i_tx_data |
40GE/50GE i_tx_data |
10GE/25GE i_tx_data |
MAC Field | Note |
---|---|---|---|---|
[511:504] | [127:120] | [63:56]' | Dest Addr[47:40] | The first octet of the Destination Address, follows Start Frame Delimiter (SFD). |
[503:496] | [119:112] | [55:48]' | Dest Addr[39:32] | |
[495:488] | [111:104] | [47:40]' | Dest Addr[31:24] | |
[495:480] | [103:96] | [39:32]' | Dest Addr[23:16] | |
[479:472] | [95:88] | [31:24]' | Dest Addr[15:8] | |
[471:464] | [87:80] | [23:16]' | Dest Addr[7:0] | |
[463:456] | [79:72] | [15:8]' | Src Addr[47:40] | When you turn on Source Address Insertion, contents are replaced by txmac_saddr unless i_tx_skip_crc is high. |
[455:448] | [71:64] | [7:0]' | Src Addr[39:32] | |
[447:440] | [63:56] | [63:56] | Src Addr[31:24] | |
[439:432] | [55:48] | [55:48] | Src Addr[23:16] | |
[431:424] | [39:32] | [47:40] | Src Addr[15:8] | |
[423:416] | [39:32] | [39:32] | Src Addr[7:0] | |
[415:408] | [31:24] | [31:24] | Length/Type[15:8] | |
[407:400] | [23:16] | [23:16] | Length/Type[7:0] | |
[399:0] | [15:0] | [15:0] | … |
Note:
- In the table above, the byte order on the bus flows from MSB to LSB, the first byte of the MAC destination address is the MSB. The MAC considers this to be the first byte after the Start Frame Delimiter (SFD).
- The bit numbered 0 is always the least significant bit of each byte.
- For example, on 100GE interface, i_tx_data[504] transmits after the SFD, and corresponds to the Ethernet destination address unicast/multicast bit.