Visible to Intel only — GUID: bhi1613757261523
Ixiasoft
Visible to Intel only — GUID: bhi1613757261523
Ixiasoft
7.13.5. PTP Status Interface
Signal Name |
Width | Description |
---|---|---|
o_tx_ptp_offset_data_valid | 1 | TX PTP offset data is valid.
When asserted, indicates that the PTP offset data for TX data path is available to read from the Avalon® memory-mapped interface registers:
The ptp_tx_lane0_calc_data_time signal is the captured time relative to the first TX SERDES lane. |
o_rx_ptp_offset_data_valid | 1 | RX PTP offset data is valid.
When asserted, indicates that the PTP offset data for RX data path is available to read from the Avalon® memory-mapped interface registers:
The ptp_rx_lane0_calc_data_time signal is the captured time relative to the first RX SERDES lane. |
o_tx_ptp_ready | 1 | TX PTP logic is ready for use. When asserted, indicates that the PTP for TX data path is fully functional and the TX egress timestamp is valid within the supported accuracy range. |
o_rx_ptp_ready | 1 | RX PTP logic is ready for use. When asserted, indicates that the PTP for RX data path is fully functional and the RX ingress timestamp is valid within the supported accuracy range. |