Visible to Intel only — GUID: igd1614810787110
Ixiasoft
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History
4.4.1. Features
4.4.2. PTP Timestamp Accuracy
4.4.3. PTP Client Flow
4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants
4.4.5. Virtual Lane Order and Offset Values
4.4.6. UI Adjustment
4.4.7. Reference Time Interval
4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
4.4.9. UI Value and PMA Delay
4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
5.1. Clock Connections in Single Instance Operation
5.2. Clock Connections in Multiple Instance Operation
5.3. Clock Connections in MAC Asynchronous FIFO Operation
5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation
5.5. Clock Connections in Synchronous Ethernet Operation
5.6. Custom Cadence
7.1. Status Interface
7.2. TX MAC Avalon ST Client Interface
7.3. RX MAC Avalon ST Aligned Client Interface
7.4. TX MAC Segmented Client Interface
7.5. RX MAC Segmented Client Interface
7.6. MAC Flow Control Interface
7.7. PCS Mode TX Interface
7.8. PCS Mode RX Interface
7.9. FlexE and OTN Mode TX Interface
7.10. FlexE and OTN Mode RX Interface
7.11. Custom Rate Interface
7.12. Reconfiguration Interfaces
7.13. Precision Time Protocol Interface
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough
7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough
7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion
7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough
7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough
7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion
7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
Visible to Intel only — GUID: igd1614810787110
Ixiasoft
9.1.5. Clocks and Resets
Name | Description |
---|---|
i_clk | Clock source with 100 MHz - 250 MHz frequency. |
i_reset | Active high reset, synchronous to i_clk clock. |
Name | Width | Description |
---|---|---|
i_kr_reconfig_addr[11:0] | 12 | Address bus for auto-negotiation and link training control and status registers (AN/LT CSRs).
|
i_kr_reconfig_read | 1 | Read enable for AN/LT CSRs. |
i_kr_reconfig_write | 1 | Write enable for AN/LT CSRs. |
i_kr_reconfig_byte_en[3:0] | 4 | AN/LT byte enable signal for writing data. |
i_kr_reconfig_writedata[31:0] | 32 | Write data for AN/LT CSRs. |
o_kr_reconfig_readdata[31:0] | 32 | Read data from AN/LT CSRs. |
o_kr_reconfig_readdata_valid | 1 | Valid signal for AN/LT CSRs read data. When asserted, the register is valid. |
o_kr_reconfig_waitrequest | 1 | Indicates that the Avalon® memory-mapped interface is busy. The read or write cycle is only complete when this signal goes low. |
Name | Width | Description |
---|---|---|
anlt_link | [NUMPORTS_GUI-1:0] | Used to connect to NUMPORTS_GUI Ethernet IP Instances. You must connect the port to the anlt_link port of the F-Tile Ethernet Intel® FPGA Hard IP.
Note: This is a virtual wire that carries no signal information used by the Intel® Quartus® Prime Tile Logic Generation flow to correctly connect the AN/LT IP to the Ethernet IP.
|