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1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History
4.4.1. Features
4.4.2. PTP Timestamp Accuracy
4.4.3. PTP Client Flow
4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants
4.4.5. Virtual Lane Order and Offset Values
4.4.6. UI Adjustment
4.4.7. Reference Time Interval
4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware)
4.4.9. UI Value and PMA Delay
4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
5.1. Clock Connections in Single Instance Operation
5.2. Clock Connections in Multiple Instance Operation
5.3. Clock Connections in MAC Asynchronous FIFO Operation
5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation
5.5. Clock Connections in Synchronous Ethernet Operation
5.6. Custom Cadence
7.1. Status Interface
7.2. TX MAC Avalon ST Client Interface
7.3. RX MAC Avalon ST Aligned Client Interface
7.4. TX MAC Segmented Client Interface
7.5. RX MAC Segmented Client Interface
7.6. MAC Flow Control Interface
7.7. PCS Mode TX Interface
7.8. PCS Mode RX Interface
7.9. FlexE and OTN Mode TX Interface
7.10. FlexE and OTN Mode RX Interface
7.11. Custom Rate Interface
7.12. Reconfiguration Interfaces
7.13. Precision Time Protocol Interface
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough
7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough
7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion
7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough
7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough
7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion
7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
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8.1. Ethernet Avalon® Memory-Mapped Interface Address Space
The Reconfiguration Ethernet interface (reconfig_eth) provides access to the Ethernet Hard IP Avalon® memory-mapped interface space for the local Ethernet Hard IP fracture, including MAC, PCS, and FEC interface, the interface to the PMA, as well as soft CSRs implemented in the FPGA fabric. All addresses are byte-based address even though the register description specifies 32 bit boundary.
Refer to the F-Tile Ethernet Hard IP Register Map to view the register map and registers description.
Register Type | Address Range |
---|---|
F-Tile EMIB Configuration Registers | 0x0000-0x00FC |
Soft Control Status Registers (Soft CSRs) | 0x0100-0x0FFC |
EHIP Registers | 0x1000-0x5FFC |
FEC/Transceiver Interface Registers | 0x6000-0x9FFC |