Visible to Intel only — GUID: sqg1600221689624
Ixiasoft
Visible to Intel only — GUID: sqg1600221689624
Ixiasoft
5.5. Clock Connections in Synchronous Ethernet Operation
The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommendations, requires that the TX clock be filtered to maintain synchronization with the RX reference clock through a sequence of nodes. The expected usage is that user logic drives the transceiver reference clocks with a filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain synchronized. In this usage model, a design component outside the IP core performs the filtering off chip.
The primary SyncE clock and the backup SyncE clock come from the recovered clock output pins of channels connected to the same SyncE network while i_clk_ref clock connects to the cleanup PLL. You can combine SyncE clocking with the data path clocking. The channels don't have to be part of the same IP core instance or same IP core variant.