F-Tile Ethernet Intel® FPGA Hard IP User Guide

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ID 683023
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Reconfiguration Interfaces 7.13. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.12. Reconfiguration Interfaces x
7.12.1. Ethernet Reconfiguration Interfaces 7.12.2. Transceiver Reconfiguration Interfaces
7.13. Precision Time Protocol Interface x
7.13.1. Time-of-Day Interface 7.13.2. TX 2-Step Timestamp Interface 7.13.3. TX 1-Step Timestamp Interface 7.13.4. RX Timestamp Interface 7.13.5. PTP Status Interface 7.13.6. PTP Tile Interface
7.13.3. TX 1-Step Timestamp Interface x
7.13.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History

1. Overview

Updated for:
Intel® Quartus® Prime Design Suite 22.1

The F-Tile Ethernet Intel® FPGA Hard IP is an Ethernet-based IP that includes a configurable, hardened protocol stack for Ethernet. The IP is compatible with the IEEE 802.3-2018 - IEEE Standard for Ethernet and the 25G/50G Ethernet Specification from the 25Gigabit Ethernet Consortium.

Table 1.  Features
Features Description
Ethernet modes with number of supported PMAs for each, where 10GE-1 is 10GE mode supporting one physical medium attachment (PMA) 1
  • 10GE-1
  • 25GE-1
  • 40GE-4
  • 50GE-2, 50GE-1
  • 100GE-4, 100GE-2, 100GE-1
  • 200GE-8, 200GE-4, 200GE-2
  • 400GE-8, 400GE-4
PMA types
  • FHT: up to four per tile 2
  • FGT: up to 16 per tile
IP core variations
  • Media Access Control (MAC) Avalon® ST
  • MAC segmented
  • Physical Coding Sublayer (PCS)
  • Optical Transportation Network (OTN)
  • Flexible Ethernet (FlexE)
Types of client interface
  • MAC Avalon® streaming interface
  • MAC segmented interface
  • Media Independent Interface (MII)
  • PCS66
Forward error correction (FEC) and Reed-Solomon FEC (RS-FEC)
  • IEEE 802.3 BASE-R Firecode (CL74)
  • IEEE 802.3 RS(528,514) (CL91)
  • IEEE 802.3 RS(544,514) (CL134)
  • Ethernet Technology Consortium (ETC) RS(272, 258)
Other
  • Support for the 1588 Precision Time Protocol (PTP)
  • Support for Auto-negotiation (AN) and Link training (LT)
  • Support for PCS lane re-ordering

The F-Tile Ethernet Intel® FPGA Hard IP core is available in the following configurations. For any variant, choose a MAC Avalon® streaming interface, a MAC segmented client interface, a PCS variation, a FlexE variation, or an OTN variation.

Table 2.  Variant Selection

FEC Selection supports the following FEC types:

  • No FEC: No FEC
  • CL74: IEEE 802.3 BASE-R Firecode (CL74)
  • CL91: IEEE 802.3 RS(528,514) (CL91)
  • CL134: IEEE 802.3 RS(544,514) (CL134)
  • ETC: Ethernet Technology Consortium ETC RS(272, 258)
Abbreviations:
  • MAC AvST: MAC Avalon® ST
  • MAC Seg: MAC Segmented
Ethernet Mode Modulation PMA Type FEC Selection MAC

AvST

 MAC

Seg

 PCS

(MII)

 PCS

(OTN/FlexE)

 PTP AN/

LT
No FEC CL74 CL91 CL134 ETC
10GE-1 NRZ FGT √ — — — — √ √ √ √ √ √
25GE-1 NRZ

FGT

FHT

 √ √ √3 √ — √ √ √ √

√4

—5

√
40GE-4 NRZ FGT √ — — — — √ √ — √ — √
50GE-2 NRZ

FGT

FHT

 √ — √ √ — √ √ √ √ √

√6

—7

50GE-1 PAM4

FGT

FHT

 — — — √ √ √ √ √ √ √ √
100GE-4 NRZ

FGT

FHT

 √ — √ √ — √ √ √ √ √

√6

—7

100GE-2 PAM4

FGT

FHT

 — — — √ √ √ √ √ √ √ √
100GE-1 PAM4 FHT — — — √ — √ √ √ √ √ √
200GE-8 NRZ FGT — — — √ — — √ √ √ √ —
200GE-4 PAM4

FGT

FHT

 — — — √ √ — √ √ √ √ √
200GE-2 PAM4 FHT — — — √ — — √ √ √ √ √
400GE-8 PAM4 FGT — — — √ √ — √ √ √ √ √
400GE-4 PAM4 FHT — — — √ — — √ √ √ √ √
Note: For reference about fractured type, refer to the Fracture Type Used by Mode table in the F-Tile Architecture User Guide.

F-Tile Ethernet Intel® FPGA Hard IP supports a variety of protocol implementations.

Table 3.  Supported Ethernet Protocols
Ethernet Channel Protocol Number of Lanes and Line Rate
10GE 10GBASE-KR 1x10.3125 Gbps NRZ lane for Copper Backplane
10GBASE-CR 1x10.3125 Gbps NRZ lane for Direct Attach Copper Cable
10GBASE-LR 1x10.3125 Gbps NRZ lane for optical fiber
25GE 25GBASE-KR 1x25.78125 Gbps NRZ lane for Copper Backplane
25GBASE-CR 1x25.78125 Gbps NRZ lane for Direct Attach Copper Cable
25GBASE-R 1x25.78125 Gbps NRZ lane based on the 25G Ethernet Consortium specification
25GAUI-1 1x25.78125 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip, Chip-to-Module
40GE 40GBASE-KR4 4x10.3125 Gbps NRZ lanes for Copper Backplane
40GBASE-CR4 4x10.3125 Gbps NRZ lanes for Direct Attach Copper Cable
40GBASE-SR4 4x10.3125 Gbps NRZ lanes for optical fiber
50GE 50GBASE-KR1 1x53.125 Gbps NRZ lane for Copper Backplane
50GBASE-CR1 1x53.125 Gbps NRZ lane for Direct Attach Copper Cable
50GBASE-KR2 2x25.78125 Gbps NRZ lane for Copper Backplane
50GBASE-CR2 2x25.78125 Gbps NRZ lane for Direct Attach Copper Cable
50GAUI-1 1x53.125 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip, Chip-to-Module
50GAUI-2 2x25.78125 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip, Chip-to-Module
100GE 100GBASE-KR1 1x106.25 Gbps PAM4 lanes for Copper Backplane
100GBASE-CR1 1x106.25 Gbps PAM4 lanes for Direct Attach Copper Cable
100GBASE-KR2 2x53.125 Gbps PAM4 lanes for Copper Backplane
100GBASE-CR2 2x53.125 Gbps PAM4 lanes for Direct Attach Copper Cable
100GBASE-KR4 4x25.78125 Gbps Non-Return-to-Zero (NRZ) lanes for Copper Backplane
100GBASE-CR4 4x25.78125 Gbps NRZ lanes for Direct Attach Copper Cable
100GAUI-1 1x106.25 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip, Chip-to-Module
100GAUI-2 2x53.125 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip, Chip-to-Module
100GAUI-4 4x26.5625 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip, Chip-to-Module
CAUI-2 2x53.125 Gbps PAM4 lanes for Low Loss Links: Chip-to-Chip, Chip-to-Module
CAUI-4 4x25.78125 Gbps NRZ lanes for Low Loss Links: Chip-to-Chip, Chip-to-Module
200GE 200GBASE-KR2 2x106.25 Gbps PAM4 lanes for Copper Backplane
200GBASE-CR2 2x106.25 Gbps PAM4 lanes for Direct Attach Copper Cable
200GBASE-KR4 4x53.125 Gbps PAM4 lanes for Copper Backplane
200GBASE-CR4 4x53.125 Gbps PAM4 lanes for Direct Attach Copper Cable
200GAUI-2 2x106.25 Gbps PAM4 for Low Loss Links: Chip-to-Chip or Chip-to-Module
200GAUI-4 4x53.125 Gbps PAM4 for Low Loss Links: Chip-to-Chip or Chip-to-Module
200GAUI-8 8x26.5265 Gbps PAM4 for Low Loss Links: Chip-to-Chip or Chip-to-Module
400GE 400GBASE-KR4 4x106.25 Gbps PAM4 lanes for Copper Backplane
400GBASE-CR4 4x106.25 Gbps PAM4 lanes for Direct Attach Copper Cable
400GAUI-4 4x106.25 Gbps PAM4 lanes for Low Loss Links: Chip-to-Chip or Chip-to-Module
400GBASE-KR8 8x53.125 Gbps PAM4 lanes for Copper Backplane (Ethernet Consortium)
400GBASE-CR8 8x53.125 Gbps PAM4 lanes for Direct Attach Copper Cable
400GAUI-8 8x53.125 Gbps PAM4 lanes for Low Loss Links: Chip-to-Chip or Chip-to-Module
Related Information
1 Ethernet modes without specified number of supported lanes assume support for all available variations for that Ethernet mode.
2 Not all FHT PMAs are bonded out in every tile. Refer to the Intel® Agilex™ Device Family Pin Connection Guidelines and Intel® Agilex™ Device Overview for exact PMA bond-out information by tile location.
3 This Ethernet mode is also compliant with IEEE 802.3 25GBASE-R RS-FEC (CL108).
4 PTP is available for no FEC, IEEE 802.3 BASE-R Firecode (CL74), and IEEE 802.3 RS(528,514) (CL91).
5 PTP is not available for IEEE 802.3 RS(544,514) (CL134).
6 Auto-negotiation and link training is available for no FEC and IEEE 802.3 RS(528,514) (CL91).
7 Auto-negotiation and link training is not available for IEEE 802.3 RS(544,514) (CL134).
Level Two Title