F-Tile Ethernet Intel® FPGA Hard IP User Guide

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Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Reconfiguration Interfaces 7.13. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.12. Reconfiguration Interfaces x
7.12.1. Ethernet Reconfiguration Interfaces 7.12.2. Transceiver Reconfiguration Interfaces
7.13. Precision Time Protocol Interface x
7.13.1. Time-of-Day Interface 7.13.2. TX 2-Step Timestamp Interface 7.13.3. TX 1-Step Timestamp Interface 7.13.4. RX Timestamp Interface 7.13.5. PTP Status Interface 7.13.6. PTP Tile Interface
7.13.3. TX 1-Step Timestamp Interface x
7.13.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History

5. Clocks

This section describes required clock connections and clock signals for various F-Tile Ethernet Intel® FPGA Hard IP core variations.
Figure 17. Conceptual Overview of General IP Core Clock ConnectionDiagram displays single Ethernet IP core and its related clock signals.

The F-Tile Reference and System PLL Clocks Intel® FPGA IP generates i_clk_ref and i_clk_sys clocks that drive the F-Tile Ethernet Intel® FPGA Hard IP (IP core).

The IP core supports the i_reconfig_clk frequency range of 100 to 250 MHz. The IP core output clock (o_clk_pll) drives both i_clk_rx and i_clk_tx input signals.

All IP core variations support the Synchronous Ethernet (SyncE) standard.

The table below describes necessary input and output clocks with required clock frequencies, and the clock-related status signals. You can use the clock status ports to hold circuits in reset or until the PLLs driving the clocks are locked.

Table 22.  Clock SignalsDescribes the input clocks you must provide, and the output clocks that the IP core provides.
Name Description
Clock Inputs
i_clk_tx TX datapath clock

This clock drives the active TX interface for the port.

This clock source is:
  • o_clk_pll clock unless you enabled Enable asynchronous adapter clocks parameter
  • o_clk_pll of the PTP tile adapter when Enable IEEE 1588 PTP parameter is enabled
i_clk_rx RX datapath clock

This clock drives the active RX interface for the port.

This clock source is:
  • o_clk_pll clock unless you enabled Enable asynchronous adapter clocks parameter
  • o_clk_pll of the PTP tile adapter when Enable IEEE 1588 PTP parameter is enabled
i_clk_pll PTP-related datapath clock

This clock drives the internal datapath clock for the port when both, Enable IEEE 1588 PTP and Enable asynchronous adapter clocks parameters, are enabled.

This clock source is the o_clk_pll output of the PTP tile adapter. You must use a single clock source when using a multiple PTP ports in your design.

Supports the following frequencies:
  • 402.83203125 MHz or higher for all Ethernet modes without FEC, with IEEE 802.3 BASE-R Firecode (CL74), or IEEE 802.3 RS(528,514) (CL91). The system PLL must be of 805.6640625 MHz frequency or higher.
  • 415.0390625 MHz or higher for all Ethernet modes with IEEE 802.3 RS(544,514) (CL134), with Ethernet Technology Consortium RS(272, 258). The system PLL must be of 830.078125 MHz frequency or higher.
  • Custom system PLL frequency supports 402.83203125 MHz or higher frequency
i_reconfig_clk Avalon® memory-mapped interface reconfiguration clock

The interface uses this clock to access control status registers (CSRs). The clock supports 100 to 250 MHz frequency.

i_clk_ref PMA reference clock
F-Tile Reference and System PLL Clock Intel® FPGA IP drives this clock.
  • 156.25 MHz is the recommended frequency. Supported when using FHT PMA or when auto-negotiation and link training is enabled.
  • 312.5 MHz when using FGT PMA without auto-negotiation and link training
  • 322.265625 MHz when using FGT PMA without auto-negotiation and link training
You must specify this frequency in the F-Tile Ethernet Intel® FPGA Hard IP PMA reference frequency IP parameter and in the F-Tile Reference and System PLL Clock Intel® FPGA IP FGT refclk frequency/FHT refclk frequency IP parameter.
Note: The i_clk_ref is a virtual signal. In simulation, the signal displays as 0.
The clock source depends on the F-Tile Ethernet Intel® FPGA Hard IP PMA selection.
  • When using FGT PMA, the clock source is the out_refclk_fgt_i output signal from the F-Tile Reference and System PLL Clocks Intel® FPGA IP.
  • When using FHT PMA, the clock source is the out_fht_cmmpll_clk_i output signal from the F-Tile Reference and System PLL Clocks Intel® FPGA IP.

Unless the Custom cadence parameter is enabled, the clock must be PPM matched to the i_clk_sys clock.

i_clk_sys Ethernet system clock

F-Tile Reference and System PLL Clock Intel® FPGA IP drives this clock.

Unless Custom cadence parameter is enabled, the clock frequency depends on the FEC type:
  • 805.6640625 MHz or higher for all Ethernet modes without FEC, or with IEEE 802.3 BASE-R Firecode (CL74), or IEEE 802.3 RS(528,514) (CL91)
  • 830.078125 MHz or higher for all Ethernet modes with IEEE 802.3 RS(544,514) (CL134), Ethernet Technology Consortium RS(272, 258)
  • 322.265625 MHz or higher is also supported for 10GE without PTP
You must specify this frequency in the F-Tile Ethernet Intel® FPGA Hard IP System PLL frequency IP parameter and in the F-Tile Reference and System PLL Clock Intel® FPGA IP Mode of system PLL IP parameter.
Note: The i_clk_sys is a virtual signal. In simulation, the signal displays as 0.

Connect to the out_systempll_clk_i signal from the F-Tile Reference and System PLL Clocks Intel® FPGA IP.

Clock Outputs
o_clk_pll System PLL clock

Clock derived from the F-Tile System PLL associated with the Ethernet IP port. The o_clk_pll frequency is equal to PLL frequency divided by 2. The following shows the o_clk_pll frequency unless you enabled custom system PLL frequency.

Supports the following frequencies:
  • 402.83203125 MHz or higher for all Ethernet modes without FEC, with IEEE 802.3 BASE-R Firecode (CL74), or IEEE 802.3 RS(528,514) (CL91). The system PLL must be of 805.6640625 MHz frequency or higher.
  • 415.0390625 MHz or higher for all Ethernet modes with IEEE 802.3 RS(544,514) (CL134), with Ethernet Technology Consortium RS(272, 258). The system PLL must be of 830.078125 MHz frequency or higher.
  • 161.1328125 MHz or higher for 10GE without enabled PTP. The system PLL must be of 322.265625 MHz frequency or higher.
  • Custom system PLL frequency divided by 2, if custom system PLL frequency is used
o_clk_tx_div
Supports the following frequencies:
  • 156.25 MHz for 10GE
  • 312.5 MHz for 40GE
  • 390.625 MHz for all other Ethernet modes

Clock recovered from the TX SERDES rate divided by either 33/66/68, depending on the FEC mode and Ethernet mode parameters. The o_clk_tx_div is equal to:

  • TX SERDES rate divided by 33 for 40GE.
  • TX SERDES rate divided by 66 when FEC mode parameter is set to one of the following:
    • None except for 40GE
    • IEEE 802.3 BASE-R Firecode (CL74)
    • IEEE 802.3 RS(528,514) (CL91)
  • TX SERDES rate divided by 68 when FEC mode parameter is set to one of the following:
    • IEEE 802.3 RS(544,514) (CL134)
    • Ethernet Technology Consortium RS(272, 258)
o_clk_rec_div64
Supports the following frequencies:
  • 161.1328125 MHz ± 200 PPM for 10GE/40GE
  • 402.83203125 MHz ± 200 PPM for Ethernet modes without FEC (except 10GE and 40GE), with IEEE 802.3 BASE-R Firecode (CL74), and IEEE 802.3 RS(528,514) (CL91)
  • 415.0390625 MHz ± 200 PPM for Ethernet modes with IEEE 802.3 RS(544,514) (CL134) and Ethernet Technology Consortium RS(272, 258)

Clock derived from RX recovered clock, divided by 64.

o_clk_rec_div
Supports the following frequencies:
  • 156.25 MHz ± 200PPM for 10GE
  • 312.50 MHz ± 200PPM for 40GE
  • 390.625 MHz ± 200PPM for all other Ethernet modes

Clock derived from the RX recovered clock divided by either 33/66/68, depending on the FEC mode parameter. The o_clk_rec_div is equal to:

  • RX SERDES rate divided by 33 for 40GE
  • RX SERDES rate divided by 66 when FEC mode parameter is set to one of the following:
    • None except for 40GE
    • IEEE 802.3 BASE-R Firecode (CL74)
    • IEEE 802.3 RS(528,514) (CL91)
  • RX SERDES rate divided by 68 when FEC mode parameter is set to one of the following:
    • IEEE 802.3 RS(544,514) (CL134)
    • Ethernet Technology Consortium RS(272, 258)
Clock Status
o_tx_pll_locked This clock indicates that the TX SERDES PLLs are locked.
Note: Do not use the o_clk_tx_div output clock until the o_tx_pll_locked signal is high.
o_cdr_lock This clock indicates that the recovered clocks are locked to data.
Note: Do not use the o_clk_rec_div64 output clock until the o_cdr_lock signal is high.

Important Design Considerations
  • In most Ethernet IP configurations, use the output clock o_clk_pll or an equivalent clock to drive the i_clk_tx and i_clk_rx signals. In asynchronous adapter option, you can use slower clocks to drive these signals.
  • PTP channel only system clock divided by 2 at frequency of 402.83 MHz or higher. When PTP is enabled, all ports with PTP enabled share the same system clock.
  • Recovered frequencies from a remote link partner are shown with ± 200 ppm range, assuming that local oscillator is ± 100ppm and remote oscillator is (unrelated) ± 100ppm. For SyncE applications, local oscillator must match recovered clock within ± 4.6ppm.

You must configure the modes in the F-Tile Reference and System PLL Clock Intel® FPGA IP. The table below displays the reference clock and output frequency based on a selected System PLL mode.

Table 23.  Mode of System PLL: System PLL Reference Clock and Output Frequencies
Mode of System PLL Reference Clock (MHz) Output Frequency (MHz)
ETHERNET_FREQ_805_156 156.25 805.6640625
ETHERNET_FREQ_805_312 312.5 805.6640625
ETHERNET_FREQ_805_322 322.265625 805.6640625
ETHERNET_FREQ_830_156 156.25 830.078125
ETHERNET_FREQ_830_312 312.5 830.078125
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