F-Tile Ethernet Intel® FPGA Hard IP User Guide

Download PDF
ID 683023
Date 3/28/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. F-Tile Ethernet Intel® FPGA Hard IP Parameters 4. Functional Description 5. Clocks 6. Resets 7. Interface Overview 8. Configuration Registers 9. Supported Modules and IPs 10. Supported Tools 11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives 12. Document Revision History
1. Overview x
1.1. Ethernet System in F-Tile Overview 1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview
1.2. F-Tile Ethernet Intel® FPGA Hard IP Overview x
1.2.1. Device Family Support 1.2.2. Device Speed Grade Support 1.2.3. Resource Utilization 1.2.4. Release Information
2. Getting Started x
2.1. Installing and Licensing F-Tile Ethernet Intel® FPGA Hard IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Reference and System PLL Clock for your IP Design 2.4. Generated File Structure 2.5. Generating Tile Files 2.6. IP Core Testbenches
2.4. Generated File Structure x
2.4.1. Generating IP-XACT File
4. Functional Description x
4.1. Datapath Description 4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC 4.3. PCS, OTN, and FlexE Modes 4.4. Precision Time Protocol 4.5. Auto-Negotiation and Link Training
4.2. F-Tile Ethernet Intel® FPGA Hard IP MAC x
4.2.1. MAC TX Datapath 4.2.2. MAC RX Datapath 4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 4.2.4. Link Fault Signaling 4.2.5. Order of Ethernet Transmission
4.2.1. MAC TX Datapath x
4.2.1.1. TX Preamble, Start, and SFD Insertion 4.2.1.2. Source Address Insertion 4.2.1.3. Length/Type Field Processing 4.2.1.4. Frame Padding 4.2.1.5. Frame Check Sequence (CRC-32) Insertion 4.2.1.6. Inter-Packet Gap Generation and Insertion
4.2.2. MAC RX Datapath x
4.2.2.1. RX Preamble Processing 4.2.2.2. RX Strict SFD Checking 4.2.2.3. RX FCS Checking 4.2.2.4. RX Malformed Packet Handling 4.2.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 4.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 4.2.2.7. Inter-Packet Gap
4.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
4.2.3.1. Conditions Triggering XOFF Frame Transmission 4.2.3.2. Conditions Triggering XON Frame Transmission 4.2.3.3. Pause Control and Generation Interface 4.2.3.4. Pause Control Frame Filtering
4.3. PCS, OTN, and FlexE Modes x
4.3.1. PCS Mode 4.3.2. OTN Mode 4.3.3. FlexE Mode
4.4. Precision Time Protocol x
4.4.1. Features 4.4.2. PTP Timestamp Accuracy 4.4.3. PTP Client Flow 4.4.4. RX Virtual Lane Offset Calculation for No FEC Variants 4.4.5. Virtual Lane Order and Offset Values 4.4.6. UI Adjustment 4.4.7. Reference Time Interval 4.4.8. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 4.4.9. UI Value and PMA Delay 4.4.10. Routing Delay Adjustment for Advanced Timestamp Accuracy Mode
4.4.3. PTP Client Flow x
4.4.3.1. PTP TX Client Flow 4.4.3.2. PTP RX Client Flow
4.4.6. UI Adjustment x
4.4.6.1. TX UI Adjustment 4.4.6.2. RX UI Adjustment
5. Clocks x
5.1. Clock Connections in Single Instance Operation 5.2. Clock Connections in Multiple Instance Operation 5.3. Clock Connections in MAC Asynchronous FIFO Operation 5.4. Clock Connections in PTP-Based Synchronous and Asynchronous Operation 5.5. Clock Connections in Synchronous Ethernet Operation 5.6. Custom Cadence
6. Resets x
6.1. Reset Signals 6.2. Reset Sequence
7. Interface Overview x
7.1. Status Interface 7.2. TX MAC Avalon ST Client Interface 7.3. RX MAC Avalon ST Aligned Client Interface 7.4. TX MAC Segmented Client Interface 7.5. RX MAC Segmented Client Interface 7.6. MAC Flow Control Interface 7.7. PCS Mode TX Interface 7.8. PCS Mode RX Interface 7.9. FlexE and OTN Mode TX Interface 7.10. FlexE and OTN Mode RX Interface 7.11. Custom Rate Interface 7.12. Reconfiguration Interfaces 7.13. Precision Time Protocol Interface
7.2. TX MAC Avalon ST Client Interface x
7.2.1. TX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.2.2. TX MAC Avalon ST Client Interface with Enabled Preamble Passthrough 7.2.3. Using MAC Avalon ST skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.2.4. Using MAC Avalon ST i_tx_error Signal to Mark Packets Invalid
7.3. RX MAC Avalon ST Aligned Client Interface x
7.3.1. RX MAC Avalon ST Client Interface with Disabled Preamble Passthrough 7.3.2. RX MAC Avalon ST Client Interface with Enabled Passthrough and RX CRC Forwarding 7.3.3. RX MAC Adapter Limitations 7.3.4. RX MAC Avalon ST Client Interface Status
7.4. TX MAC Segmented Client Interface x
7.4.1. TX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.4.2. TX MAC Segmented Client Interface with Enabled Preamble Passthrough 7.4.3. Using MAC Segmented skip_crc Signal to Control Source Address, PAD, and CRC Insertion 7.4.4. Using MAC Segmented i_tx_mac_error to Mark Packets Invalid
7.5. RX MAC Segmented Client Interface x
7.5.1. RX MAC Segmented Client Interface with Disabled Preamble Passthrough 7.5.2. RX MAC Segmented Client Interface with Enabled Passthrough and RX CRC Forwarding 7.5.3. RX MAC Segmented Client Interface Status and Errors
7.12. Reconfiguration Interfaces x
7.12.1. Ethernet Reconfiguration Interfaces 7.12.2. Transceiver Reconfiguration Interfaces
7.13. Precision Time Protocol Interface x
7.13.1. Time-of-Day Interface 7.13.2. TX 2-Step Timestamp Interface 7.13.3. TX 1-Step Timestamp Interface 7.13.4. RX Timestamp Interface 7.13.5. PTP Status Interface 7.13.6. PTP Tile Interface
7.13.3. TX 1-Step Timestamp Interface x
7.13.3.1. PTP Field Offset for 1-Step Operation
8. Configuration Registers x
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space 8.2. Transceiver Avalon® Memory-Mapped Interface Address Space
8.1. Ethernet Avalon® Memory-Mapped Interface Address Space x
8.1.1. Ethernet Hard IP Core CSRs 8.1.2. FEC and Transceiver Control and Status Registers
9. Supported Modules and IPs x
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP 9.2. PTP Tile Adapter
9.1. F-Tile Auto-Negotiation and Link Training For Ethernet Intel® FPGA IP x
9.1.1. Overview 9.1.2. Release Information 9.1.3. Functional Description 9.1.4. Parameters 9.1.5. Clocks and Resets 9.1.6. Registers
9.2. PTP Tile Adapter x
9.2.1. Overview 9.2.2. Clocks, Reset, and Interface Ports 9.2.3. PTP Asymmetry Delay Reconfiguration Interface 9.2.4. PTP Peer-to-Peer MeanPathDelay Reconfiguration Interface
10. Supported Tools x
10.1. F-Tile Channel Placement Tool 10.2. Ethernet Toolkit Overview
10.2. Ethernet Toolkit Overview x
10.2.1. Features
1. Overview
2. Getting Started
3. F-Tile Ethernet Intel® FPGA Hard IP Parameters
4. Functional Description
5. Clocks
6. Resets
7. Interface Overview
8. Configuration Registers
9. Supported Modules and IPs
10. Supported Tools
11. F-Tile Ethernet Intel® FPGA Hard IP User Guide Archives
12. Document Revision History

7.13.2. TX 2-Step Timestamp Interface

The timestamp interface signals are valid when i_tx_valid and i_tx_startofpacket signals are high. To initiate a timestamp request, the i_ptp_ts_req signal must be high. You also must specify a fingerprint value in the i_ptp_fp signal. The fingerprint values are re-usable once the IP core returns a packet with the timestamp.

Figure 49. Using the IEEE 1588 TX 2-Step Timestamp Interface The figure depicts transmission of two packets. The first packet contains a 2-step timestamp request with assigned FP1 fingerprint value.

When the IP core returns the timestamp for a packet with a 2-step timestamp request, it asserts the o_ptp_ets_valid signal to indicate that the o_ptp_ets and o_ptp_ets_fp signals contain the timestamp information. The o_ptp_ets contains the timestamp and the o_ptp_ets_fp signal indicates the specific packet the timestamp is for. The IP processes the timestamp requests in the order they were received.

Figure 50. 2-Step Timestamp: Receiving Packet with TimestampThe figure shows that the IP received the timestamp for packet FP1 and then sometime later, IP returns the timestamp for packet FP2.
Table 56.  Signals of the 2-Step TX Timestamp InterfaceThe timestamp is always in 1588 v2 format.

All interface signals are synchronous and clocked by the i_clk_tx clock.

Signal Name

Width

Description

i_ptp_ts_req

i_ptp_ts_req[1:0]

1 bit (10GE/25GE/50GE/100GE/200GE)

2 bits (400GE)

 Request a 2-step timestamp signal for the current TX packet when Ethernet rate is 10GE/25GE/50GE/100GE/200GE/400GE.
  • For TX MAC Avalon ST client interface, i_ptp_ts_req[0] is valid only when both, i_tx_valid and i_tx_startofpacket signals, are equal to 1.
  • For TX MAC segmented client interface, i_ptp_ts_req[0] is valid only when i_tx_mac_valid is equal to 1 and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_ts_req[1] is valid only when i_tx_mac_valid is equal to 1 and i_tx_mac_inframe[15:8] contains the SOP.

i_ptp_fp[w],

where w represents timestamp fingerprint width

i_ptp_fp[w*2],

where w is 8-12

w bit (10GE/25GE/50GE/100GE/200GE)

(w*2) bits (400GE)

Fingerprint signal for current TX packet when Ethernet rate is 10GE/ 25GE/50GE/100GE/200GE/400GE.

Assigns an 8 bit fingerprint to a TX packet that is being transmitted so the returned TX egress timestamp can be identified with respective TX packet.

  • For TX MAC Avalon ST client interface, i_ptp_fp[(w-1):0] is valid only when both, i_tx_valid and i_tx_startofpacket signals, are equal to 1.
  • For TX MAC segmented client interface, i_ptp_fp[(w-1):0] is valid only when i_tx_mac_valid is equal to 1 and i_tx_mac_inframe[7:0] contains the start of the packet (SOP).

    The i_ptp_fp[w*2-1:w] is valid only when i_tx_mac_valid is equal to 1 and i_tx_mac_inframe[15:8] contains the SOP.

Used for both 2-step and 1-step PTP packets.

Intel recommends to use large range of fingerprints to avoid assigning same fingerprint to two currently processed TX packets.

o_ptp_ets_valid

o_ptp_ets_valid[1:0]

1 bit (10GE/25GE/50GE/100GE/200GE)

2 bits (400GE)

 TX egress timestamp valid signal when Ethernet rate is 10GE/ 25GE/50GE/100GE/200GE/400GE.

o_ptp_ets[95:0]

o_ptp_ets[191:0]

96 bits (10GE/25GE/50GE/100GE/200GE

192 bits (400GE)

 TX egress timestamp bus when Ethernet rate is 10GE/ 25GE/50GE/100GE/200GE/400GE.
The bus presents an egress timestamp for the TX packet transmitted with the fingerprint given by o_ptp_ets_fp signal.
  • o_ptp_ets[95:0] is valid only when o_ptp_ets_valid[0]=1.
  • o_ptp_ets[191:96] is valid only when o_ptp_ets_valid[1]=1.

The egress timestamp applies for 2-step and 1-step PTP packets.

o_ptp_ets_fp[w]

o_ptp_ets_fp[w*2],

where w is 8-12

w bits (10GE/25GE/50GE/100GE/200GE)

(w*2) bits (400GE)

TX egress timestamp fingerprint when Ethernet rate is 10GE/25GE/ 50GE/100GE/200GE/400GE.
The bus presents the fingerprint for the current 2-step egress timestamp. You use the fingerprint to determine which TX packet the timestamp belongs to.
  • o_ptp_ets_fp[w-1:0] is valid only when o_ptp_ets_valid[0] = 1.
  • o_ptp_ets_fp[w*2-1:w] is valid only when o_ptp_ets_valid[1] = 1.

The egress timestamp applies for 2-step and 1-step PTP packets.

Level Two Title