sys_mgr_core Address Map

Module Instance Base Address End Address
i_sys_mgr_core 0xFFD06000 0xFFD061FF
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Register Offset Width Access Reset Value Description
siliconid1 0x0 32 RO 0x10002 
Silicon ID1 Register
siliconid2 0x4 32 RO 0x0 
Silicon ID2 Register
wddbg 0x8 32 RW 0xF 
L4 Watchdog Debug Register
bootinfo 0xC 32 RO 0x0 
Boot Info Register
mpu_ctrl_l2_ecc 0x10 32 RW 0x0 
L2 Data RAM ECC Enable Register
dma 0x20 32 RW 0x100 
Control Register
dma_periph 0x24 32 RW 0x0 
Peripheral Security Register
sdmmc 0x28 32 RW 0x0 
Control Register
sdmmc_l3master 0x2C 32 RW 0x3 
SD/MMC L3 Master HPROT Register
nand_bootstrap 0x30 32 RW 0x0 
Bootstrap Control Register
nand_l3master 0x34 32 RW 0x0 
NAND L3 Master AxCACHE Register
usb0_l3master 0x38 32 RW 0x1 
USB L3 Master HPROT Register
usb1_l3master 0x3C 32 RW 0x1 
USB L3 Master HPROT Register
emac_global 0x40 32 RW 0x0 
EMAC L3 Master AxCACHE Register
emac0 0x44 32 RW 0x12000003 
Control Register
emac1 0x48 32 RW 0x12000003 
Control Register
emac2 0x4C 32 RW 0x12000003 
Control Register
fpgaintf_en_global 0x60 32 RW 0x1 
Global Disable Register
fpgaintf_en_0 0x64 32 RW 0xFFFFFFFF 
FPGA interface Individual Enable Register
fpgaintf_en_1 0x68 32 RW 0xFFFFFFFF 
FPGA interface Individual Enable Register
fpgaintf_en_2 0x6C 32 RW 0x0 
FPGA interface Individual Enable Register
fpgaintf_en_3 0x70 32 RW 0x0 
FPGA interface Individual Enable Register
noc_addr_remap_value 0x80 32 RW 0x0 
Address remap register. This register drives the remap bits for the NOC.

This is read / write register.
noc_addr_remap_set 0x84 32 WO 0x0 
This is a Write 1 to Set register.
Writing 0 is ignored, and writing 1 to a specific bit field sets the specific remap bit.
Reads should not return an error, but the actual read value is "Undefined" .
noc_addr_remap_clear 0x88 32 WO 0x0 
This is a Write 1 to Clear register.
Writing 0 is ignored, and writing 1 to a specific bit field Clears the specific remap bit.
Reads should not return an error, but the actual read value is "Undefined" .
ecc_intmask_value 0x90 32 RW 0x0 
ECC interrupt mask register.
This is a read/write register.
ecc_intmask_set 0x94 32 WO 0x0 
ECC interrupt mask Set register
ecc_intmask_clr 0x98 32 WO 0x0 
ECC interrupt mask Clear register
ecc_intstatus_serr 0x9C 32 RO 0x0 
ECC single bit error status of individual modules.
A write to this register should return an error.
ecc_intstatus_derr 0xA0 32 RO 0x0 
ECC double bit error status of individual modules.
A write to this register should return an error.
mpu_status_l2_ecc 0xA4 32 RO 0x0 
This is a read only register which reads the current mpu L2 ecc interrupt status.
A write to this register should return an error.
mpu_clear_l2_ecc 0xA8 32 RW 0x0 
Write 1 to Clear register to clear the specific bit field of mpu l2 ecc interrupt pending status
Reads should not return an error, but the read value is undefined.
mpu_status_l1_parity 0xAC 32 RO 0x0 
Parity status from L1 and scu. This is a read only register.
A write to this register should return an error.

[17] CPU1 SCU parity error
[16] CPU0 SCU parity error

[15] CPU1 BTAC parity error
[14] CPU1 GHB parity error
[13] CPU1 instruction tag RAM parity error
[12] CPU1 instruction data RAM parity error
[11] CPU1 main TLB parity error
[10] CPU1 data outer RAM parity error
[9]  CPU1 data tag RAM parity error
[8]  CPU1 data data RAM parity error.

[7]  CPU0 BTAC parity error
[6]  CPU0 GHB parity error
[5]  CPU0 instruction tag RAM parity error
[4]  CPU0 instruction data RAM parity error
[3]  CPU0 main TLB parity error
[2]  CPU0 data outer RAM parity error
[1]  CPU0 data tag RAM parity error
[0]  CPU0 data data RAM parity error.
mpu_clear_l1_parity 0xB0 32 RW 0x0 
Parity status clear bit.
A write to 1 of a specific bit clears the curresponding parity status bit.
A read of this register should not return an error, but the actual read value is undefined.

[17] CPU1 SCU parity error
[16] CPU0 SCU parity error

[15] CPU1 BTAC parity error
[14] CPU1 GHB parity error
[13] CPU1 instruction tag RAM parity error
[12] CPU1 instruction data RAM parity error
[11] CPU1 main TLB parity error
[10] CPU1 data outer RAM parity error
[9]  CPU1 data tag RAM parity error
[8]  CPU1 data data RAM parity error.

[7]  CPU0 BTAC parity error
[6]  CPU0 GHB parity error
[5]  CPU0 instruction tag RAM parity error
[4]  CPU0 instruction data RAM parity error
[3]  CPU0 main TLB parity error
[2]  CPU0 data outer RAM parity error
[1]  CPU0 data tag RAM parity error
[0]  CPU0 data data RAM parity error.
mpu_set_l1_parity 0xB4 32 RW 0x0 
Parity status set bit.
A write to 1 of a specific bit sets the curresponding parity status bit.
This register is used only to check the specific ISR routine.
A read of this register should not return an error, but the actual read value is undefined.

[17] CPU1 SCU parity error
[16] CPU0 SCU parity error

[15] CPU1 BTAC parity error
[14] CPU1 GHB parity error
[13] CPU1 instruction tag RAM parity error
[12] CPU1 instruction data RAM parity error
[11] CPU1 main TLB parity error
[10] CPU1 data outer RAM parity error
[9]  CPU1 data tag RAM parity error
[8]  CPU1 data data RAM parity error.

[7]  CPU0 BTAC parity error
[6]  CPU0 GHB parity error
[5]  CPU0 instruction tag RAM parity error
[4]  CPU0 instruction data RAM parity error
[3]  CPU0 main TLB parity error
[2]  CPU0 data outer RAM parity error
[1]  CPU0 data tag RAM parity error
[0]  CPU0 data data RAM parity error.
noc_timeout 0xC0 32 RW 0x0 





noc_idlereq_set
0xC4
32
WO
0x0

Set IDLE request to each NOC master.





noc_idlereq_clr
0xC8
32
WO
0x0

Clear IDLE request to each NOC master.





noc_idlereq_value
0xCC
32
'not specified'
0x0

IDLE request to each NOC master.

This register can be set by writing 1 to the specific bit in noc_idlereq_set register.
This register can be cleared by writing 1 to the specific bit in noc_idlereq_clr register





noc_idleack
0xD0
32
RO
0x0

Idle acknowledge value from NOC Masters. This is asserted (value 1 in the field) in response to the IDLE requests asserted by software.





noc_idlestatus
0xD4
32
RO
0x0

Status of IDLE from the NOC masters. A 1 in the field means the specific master is idle.





fpga2soc_ctrl
0xD8
32
RW
0x0