sdmmc_l3master

         Controls the L3 master HPROT AHB-Lite signal.
These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation
All fields are reset by a cold or warm reset.

Module Instance	Base Address	Register Address
`i_sys_mgr_core`	`0xFFD06000`	`0xFFD0602C`

Offset: 0x2C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`											`hprot` `RW 0x3`

sdmmc_l3master Fields

Bit	Name	Description	Access	Reset
4:0	`hprot`	========================== HPROT[4] Allocate 0: L3 master accesses for the module are non-allocatable 1: L3 master accesses for the module are allocatable ========================== HPROT[3] Cachable 0: L3 master accesses for the module are non-cacheable. 1: L3 master accesses for the module are cacheable. ========================== HPROT[2] Bufferable 0: L3 master accesses for the module are not bufferable. 1: L3 master accesses for the module are bufferable. ========================== HPROT[1] Privileged 0: L3 master accesses for the module are not privileged. 1: L3 master accesses for the module are privileged. ========================== HPROT[0] Data/Opcode 0: Specifies if the L3 master access is for opcode 1: Specifies if the L3 master access is for data ========================== HPROT[4:2] Example Encodings ========================== 0 0 0 Strongly Ordered, cannot be buffered 0 0 1 Device, can be buffered 0 1 0 Cachable (Outer Noncachable, do not allocate on reads or writes) 1 1 0 Cachable Write-Through (allocate on reads only, no allocate on write) 0 1 1 Cachable Write-Back (allocate on reads and writes) 1 1 1 Cachable Write-Back (allocate on reads only, no allocate on write) ========================== HPROT[1:0] Example Encodings ========================== - 0 Opcode Fetch - 1 Data Access 0 - User Access 1 - Privileged Access ==========================	`RW`	`0x3`

Bit

Name

Description

Access

Reset

4:0

hprot

==========================
HPROT[4] Allocate
  0: L3 master accesses for the module are non-allocatable
  1: L3 master accesses for the module are allocatable
==========================
HPROT[3] Cachable
  0: L3 master accesses for the module are non-cacheable.
  1: L3 master accesses for the module are cacheable.
==========================
HPROT[2] Bufferable
  0: L3 master accesses for the module are not bufferable.
  1: L3 master accesses for the module are bufferable.
==========================
HPROT[1] Privileged
  0: L3 master accesses for the module are not privileged.
  1: L3 master accesses for the module are privileged.
==========================
HPROT[0] Data/Opcode
  0: Specifies if the L3 master access is for opcode
  1: Specifies if the L3 master access is for data
==========================
HPROT[4:2] Example Encodings
==========================
0	0	0	Strongly Ordered, cannot be buffered
0	0	1	Device, can be buffered
0	1	0	Cachable (Outer Noncachable, do not allocate on reads or writes)
1	1	0	Cachable Write-Through (allocate on reads only, no allocate on write)
0	1	1	Cachable Write-Back (allocate on reads and writes)
1	1	1	Cachable Write-Back (allocate on reads only, no allocate on write)
==========================
HPROT[1:0] Example Encodings
==========================
-	0	Opcode Fetch
-	1	Data Access
0	-	User Access
1	-	Privileged Access
==========================

RW

0x3