bootinfo

         Provides access to boot configuration information.
This is a read only register and a write should return error.
This register gets reset only on a cold reset.

Module Instance	Base Address	Register Address
`i_sys_mgr_core`	`0xFFD06000`	`0xFFD0600C`

Offset: 0xC

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`	`bsel` `RO 0x0`			`Reserved`	`pin_bsel` `RO 0x0`			`Reserved`	`fpga_bsel` `RO 0x0`			`Reserved`			`fpga_bsel_en` `RO 0x0`

bootinfo Fields

Bit

Name

Description

Access

Reset

14:12

bsel

Multiplexed Value of Boot Select from pins and fpga

Value	Description
0	RESERVEDx
1	FPGA
2	NAND_Flash_1_8v
3	NAND_Flash_3_0v
4	SD_MMC_EXTERNAL_TRANSCEIVER_1_8v
5	SD_MMC_INTERNAL_TRANSCEIVER_3_0v
6	QSPI_Flash_1_8v
7	QSPI_Flash_3_0v

RO

0x0

10:8

pin_bsel

Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are sampled upon deassertion of cold reset.

Value	Description
0	RESERVEDx
1	FPGA
2	NAND_Flash_1_8v
3	NAND_Flash_3_0v
4	SD_MMC_EXTERNAL_TRANSCEIVER_1_8v
5	SD_MMC_INTERNAL_TRANSCEIVER_3_0v
6	QSPI_Flash_1_8v
7	QSPI_Flash_3_0v

RO

0x0

6:4

fpga_bsel

The boot select field specifies the boot source. It is read by the Boot ROM code on a cold or warm reset to determine the boot source.

The boot select value is equal to the f2s_bsel signal from the FPGA if the f2s_bsel_en signal from the FPGA is 1 or equal to the sampled value of HPS BSEL pins if the f2s_bsel_en signal from the FPGA is 0 or the FPGA is not powered on or not in User Mode (fpga_config_complete = 0).
The HPS BSEL pins value are sampled upon deassertion of cold reset.

Value	Description
0	RESERVEDx
1	FPGA
2	NAND_Flash_1_8v
3	NAND_Flash_3_0v
4	SD_MMC_EXTERNAL_TRANSCEIVER_1_8v
5	SD_MMC_INTERNAL_TRANSCEIVER_3_0v
6	QSPI_Flash_1_8v
7	QSPI_Flash_3_0v

RO

0x0

fpga_bsel_en

Specifies the value of the f2s_bsel_en. f2s_bsel_en is a signal from FPGA.
 If 1, boot select value is equal to FPGA boot select signal (f2s_bsel).
If 0, boot select value is equal to the sampled value of HPS BSEL pins.
Value of f2s_bsel_en is overidden to 0x0 if FPGA is not in user mode (fpga_config_complete = 0)

RO

0x0