sdmmc
Registers used by the SDMMC Controller. All fields are reset by a cold or warm reset.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_sys_mgr_core | 0xFFD06000 | 0xFFD06028 |
Offset: 0x28
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
smplsel RW 0x0 |
Reserved |
drvsel RW 0x0 |
||||||||||||
sdmmc Fields
| Bit | Name | Description | Access | Reset | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 6:4 | smplsel | Select which phase shift of the clock for cclk_in_sample. Note that the boot ROM programs this field to 0x0.
|
RW | 0x0 | ||||||||||||||||||
| 2:0 | drvsel | Select which phase shift of the clock for cclk_in_drv. Note that the boot ROM programs this field to 0x3.
|
RW | 0x0 |