mpu_clear_l2_ecc

         Write 1 to Clear register to clear the specific bit field of mpu l2 ecc interrupt pending status
Reads should not return an error, but the read value is undefined.

Module Instance	Base Address	Register Address
`i_sys_mgr_core`	`0xFFD06000`	`0xFFD060A8`

Offset: 0xA8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`merr` `0x0`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`serr` `0x0`	`Reserved`

mpu_clear_l2_ecc Fields

Bit	Name	Description	Access	Reset
31	`merr`	Write 1 to this field to clear the MPU L2 ECC multiple bit Error interrupt Status and the actual Interrupt.	`RW`	`0x0`
15	`serr`	Write 1 to this field to clear the MPU L2 ECC single bit Error interrupt Status and the actual Interrupt.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

merr

Write 1 to this field to clear the MPU L2 ECC multiple bit Error interrupt Status and the actual Interrupt.

RW

0x0

serr

Write 1 to this field to clear the MPU L2 ECC single bit Error interrupt Status and the actual Interrupt.

RW

0x0