wddbg
Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These control registers are used to drive the pause input signal of the L4 watchdogs. Note that the watchdogs built into the MPU automatically are paused when their associated CPU enters debug mode. Only reset by a cold reset.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_sys_mgr_core | 0xFFD06000 | 0xFFD06008 |
Offset: 0x8
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
mode_1 RW 0x3 |
mode_0 RW 0x3 |
|||||||||||||
wddbg Fields
| Bit | Name | Description | Access | Reset | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 3:2 | mode_1 | Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
|
RW | 0x3 | ||||||||||
| 1:0 | mode_0 | Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.
|
RW | 0x3 |