sys_mgr_core Summary

Base Address: 0xFFD06000

Register Address Offset	Bit Fields
`i_sys_mgr_core`
`siliconid1` `0x0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`id` `RO 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rev` `RO 0x2`
`siliconid2` `0x4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`rsv` `RO 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`rsv` `RO 0x0`
`wddbg` `0x8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`mode_1` `RW 0x3`		`mode_0` `RW 0x3`
`bootinfo` `0xC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`	`bsel` `RO 0x0`			`Reserved`	`pin_bsel` `RO 0x0`			`Reserved`	`fpga_bsel` `RO 0x0`			`Reserved`			`fpga_bsel_en` `RO 0x0`
`mpu_ctrl_l2_ecc` `0x10`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`															`inj_type` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`inj_en` `RW 0x0`	`Reserved`							`ecc_en` `RW 0x0`
`dma` `0x20`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`irq_ns` `RW 0x0`								`Reserved`							`mgr_ns` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`chansel_2` `RW 0x1`	`Reserved`			`chansel_1` `RW 0x0`	`Reserved`			`chansel_0` `RW 0x0`
`dma_periph` `0x24`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`ns` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`ns` `RW 0x0`
`sdmmc` `0x28`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`									`smplsel` `RW 0x0`			`Reserved`	`drvsel` `RW 0x0`
`sdmmc_l3master` `0x2C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`											`hprot` `RW 0x3`
`nand_bootstrap` `0x30`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`			`page512_x16` `RW 0x0`	`Reserved`			`page512` `RW 0x0`	`Reserved`							`tworowaddr` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`noloadb0p0` `RW 0x0`	`Reserved`							`noinit` `RW 0x0`
`nand_l3master` `0x34`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`								`awcache_0` `RW 0x0`				`arcache_0` `RW 0x0`
`usb0_l3master` `0x38`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`hprot` `RW 0x1`
`usb1_l3master` `0x3C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`												`hprot` `RW 0x1`
`emac_global` `0x40`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`ptp_clk_sel` `RW 0x0`
`emac0` `0x44`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`axi_disable` `RW 0x0`	`sbd_data_endianness` `RW 0x0`	`Reserved`	`awprot` `RW 0x2`		`Reserved`	`arprot` `RW 0x2`		`awcache` `RW 0x0`				`arcache` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`ptp_ref_sel` `RW 0x0`	`Reserved`						`phy_intf_sel` `RW 0x3`
`emac1` `0x48`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`axi_disable` `RW 0x0`	`sbd_data_endianness` `RW 0x0`	`Reserved`	`awprot` `RW 0x2`		`Reserved`	`arprot` `RW 0x2`		`awcache` `RW 0x0`				`arcache` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`ptp_ref_sel` `RW 0x0`	`Reserved`						`phy_intf_sel` `RW 0x3`
`emac2` `0x4C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`axi_disable` `RW 0x0`	`sbd_data_endianness` `RW 0x0`	`Reserved`	`awprot` `RW 0x2`		`Reserved`	`arprot` `RW 0x2`		`awcache` `RW 0x0`				`arcache` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`ptp_ref_sel` `RW 0x0`	`Reserved`						`phy_intf_sel` `RW 0x3`
`fpgaintf_en_global` `0x60`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`intf` `RW 0x1`
`fpgaintf_en_0` `0x64`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`															`bscan` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`cfgio` `RW 0x1`	`Reserved`							`rstreq` `RW 0x1`
`fpgaintf_en_1` `0x68`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`ctmtrigger` `RW 0x1`	`Reserved`							`stmevent` `RW 0x1`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`dbgapb` `RW 0x1`	`Reserved`			`trace` `RW 0x1`	`Reserved`
`fpgaintf_en_2` `0x6C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`spim_1` `RW 0x0`	`Reserved`							`spim_0` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`sdmmc` `RW 0x0`	`Reserved`			`nand` `RW 0x0`	`Reserved`
`fpgaintf_en_3` `0x70`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`															`emac_2` `RW 0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`emac_1` `RW 0x0`	`Reserved`							`emac_0` `RW 0x0`
`noc_addr_remap_value` `0x80`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`remap1` `0x0`	`remap0` `0x0`
`noc_addr_remap_set` `0x84`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`remap1` `0x0`	`remap0` `0x0`
`noc_addr_remap_clear` `0x88`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`														`remap1` `0x0`	`remap0` `0x0`
`ecc_intmask_value` `0x90`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`													`ddr1` `0x0`	`ddr0` `0x0`	`sdmmcb` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmca` `0x0`	`qspi` `0x0`	`nand_rd` `0x0`	`nand_wr` `0x0`	`nand_buf` `0x0`	`dma` `0x0`	`emac2_tx` `0x0`	`emac2_rx` `0x0`	`emac1_tx` `0x0`	`emac1_rx` `0x0`	`emac0_tx` `0x0`	`emac0_rx` `0x0`	`usb1` `0x0`	`usb0` `0x0`	`ocram` `0x0`	`l2` `0x0`
`ecc_intmask_set` `0x94`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`													`ddr1` `0x0`	`ddr0` `0x0`	`sdmmcb` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmca` `0x0`	`qspi` `0x0`	`nand_rd` `0x0`	`nand_wr` `0x0`	`nand_buf` `0x0`	`dma` `0x0`	`emac2_tx` `0x0`	`emac2_rx` `0x0`	`emac1_tx` `0x0`	`emac1_rx` `0x0`	`emac0_tx` `0x0`	`emac0_rx` `0x0`	`usb1` `0x0`	`usb0` `0x0`	`ocram` `0x0`	`l2` `0x0`
`ecc_intmask_clr` `0x98`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`													`ddr1` `0x0`	`ddr0` `0x0`	`sdmmcb` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmca` `0x0`	`qspi` `0x0`	`nand_rd` `0x0`	`nand_wr` `0x0`	`nand_buf` `0x0`	`dma` `0x0`	`emac2_tx` `0x0`	`emac2_rx` `0x0`	`emac1_tx` `0x0`	`emac1_rx` `0x0`	`emac0_tx` `0x0`	`emac0_rx` `0x0`	`usb1` `0x0`	`usb0` `0x0`	`ocram` `0x0`	`l2` `0x0`
`ecc_intstatus_serr` `0x9C`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`													`ddr1` `0x0`	`ddr0` `0x0`	`sdmmcb` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmca` `0x0`	`qspi` `0x0`	`nand_rd` `0x0`	`nand_wr` `0x0`	`nand_buf` `0x0`	`dma` `0x0`	`emac2_tx` `0x0`	`emac2_rx` `0x0`	`emac1_tx` `0x0`	`emac1_rx` `0x0`	`emac0_tx` `0x0`	`emac0_rx` `0x0`	`usb1` `0x0`	`usb0` `0x0`	`ocram` `0x0`	`l2` `0x0`
`ecc_intstatus_derr` `0xA0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`													`ddr1` `0x0`	`ddr0` `0x0`	`sdmmcb` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`sdmmca` `0x0`	`qspi` `0x0`	`nand_rd` `0x0`	`nand_wr` `0x0`	`nand_buf` `0x0`	`dma` `0x0`	`emac2_tx` `0x0`	`emac2_rx` `0x0`	`emac1_tx` `0x0`	`emac1_rx` `0x0`	`emac0_tx` `0x0`	`emac0_rx` `0x0`	`usb1` `0x0`	`usb0` `0x0`	`ocram` `0x0`	`l2` `0x0`
`mpu_status_l2_ecc` `0xA4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`merr_pending` `0x0`	`Reserved`			`merr_info` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`serr_pending` `0x0`	`Reserved`			`serr_info` `0x0`
`mpu_clear_l2_ecc` `0xA8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`merr` `0x0`	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`serr` `0x0`	`Reserved`
`mpu_status_l1_parity` `0xAC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`														`scu` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cpu1` `0x0`								`cpu0` `0x0`
`mpu_clear_l1_parity` `0xB0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`														`scu` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cpu1` `0x0`								`cpu0` `0x0`
`mpu_set_l1_parity` `0xB4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`														`scu` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`cpu1` `0x0`								`cpu0` `0x0`
`noc_timeout` `0xC0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`en` `0x0`
`noc_idlereq_set` `0xC4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`fpga2sdram2` `0x0`	`Reserved`			`fpga2sdram1` `0x0`	`Reserved`			`fpga2sdram0` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`fpga2soc` `0x0`	`Reserved`			`lwsoc2fpga` `0x0`	`Reserved`			`soc2fpga` `0x0`
`noc_idlereq_clr` `0xC8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`fpga2sdram2` `0x0`	`Reserved`			`fpga2sdram1` `0x0`	`Reserved`			`fpga2sdram0` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`fpga2soc` `0x0`	`Reserved`			`lwsoc2fpga` `0x0`	`Reserved`			`soc2fpga` `0x0`
`noc_idlereq_value` `0xCC`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`fpga2sdram2` `0x0`	`Reserved`			`fpga2sdram1` `0x0`	`Reserved`			`fpga2sdram0` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`fpga2soc` `0x0`	`Reserved`			`lwsoc2fpga` `0x0`	`Reserved`			`soc2fpga` `0x0`
`noc_idleack` `0xD0`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`fpga2sdram2` `0x0`	`Reserved`			`fpga2sdram1` `0x0`	`Reserved`			`fpga2sdram0` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`fpga2soc` `0x0`	`Reserved`			`lwsoc2fpga` `0x0`	`Reserved`			`soc2fpga` `0x0`
`noc_idlestatus` `0xD4`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`							`fpga2sdram2` `0x0`	`Reserved`			`fpga2sdram1` `0x0`	`Reserved`			`fpga2sdram0` `0x0`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`							`fpga2soc` `0x0`	`Reserved`			`lwsoc2fpga` `0x0`	`Reserved`			`soc2fpga` `0x0`
`fpga2soc_ctrl` `0xD8`	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	`Reserved`
	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	`Reserved`															`allow_secure` `0x0`