fpga_mgr_fpgamgrregs Address Map

Module Instance	Base Address	End Address
`i_fpga_mgr_fpgamgrregs`	`0xFFD03000`	`0xFFD03FFF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`dclkcnt`	`0x8`	`32`	`RW`	`0x0`	DCLK Count Register
`dclkstat`	`0xC`	`32`	`RW`	`0x0`	DCLK Status Register
`gpo`	`0x10`	`32`	`RW`	`0x0`	General-Purpose Output Register
`gpi`	`0x14`	`32`	`RO`	`0x0`	General-Purpose Input Register
`misci`	`0x18`	`32`	`RO`	`0x0`	Miscellaneous Input Register
`emr_data0`	`0x30`	`32`	`RO`	`0x0`	Extracted EMR register content
`emr_data1`	`0x34`	`32`	`RO`	`0x0`	Extracted EMR register content
`emr_data2`	`0x38`	`32`	`RO`	`0x`	bits [95:64] of EMR register
`emr_data3`	`0x3C`	`32`	`RO`	`0x`	bits [119:96] of EMR register
`emr_data4`	`0x40`	`32`	`RO`	`0x`	bits [159:128] of EMR register
`emr_data5`	`0x44`	`32`	`RO`	`0x`	bits [171:160] of EMR register
`emr_valid`	`0x48`	`32`	`RW`	`0x0`
`emr_en`	`0x4C`	`32`	`RW`	`0x77000000`
`jtag_config`	`0x50`	`32`	`RW`	`0x1400`	Scan-Chain Enable Register
`jtag_status`	`0x54`	`32`	`RO`	`0x500`	Control/Status Word Register
`jtag_kick`	`0x58`	`32`	`WO`	`0x0`	TCK Divide ratio
`jtag_data_w`	`0x60`	`32`	`WO`	`0x0`	TX FIFO Write
`jtag_data_r`	`0x64`	`32`	`RO`	`0x0`	RX FIFO Read
`imgcfg_ctrl_00`	`0x70`	`32`	`RW`	`0x107`
`imgcfg_ctrl_01`	`0x74`	`32`	`RW`	`0x1000001`
`imgcfg_ctrl_02`	`0x78`	`32`	`RW`	`0x200`	Control Register
`imgcfg_stat`	`0x80`	`32`	`RO`	`0x1000000`	This is the unmasked status. Value of corresponding inputs from CSS or PINs, without considering the intr_mask or intr_polarity.
`intr_masked_status`	`0x84`	`32`	`RW`	`0x0`	When you read this register you read the active high pending interrupt status of corresponding bit. This value is after the masking specified by intr_mask and after the polarity conversion as specified in intr_polarity
`intr_mask`	`0x88`	`32`	`RW`	`0x33073FFF`	Mask for interrupts. A value of 1 in a particular bit will cause the specific interrupt to be masked.
`intr_polarity`	`0x8C`	`32`	`RW`	`0x33073FFF`	Active Level of the signal to generate interrupt. 0 :Active LOW. An interrupt will be generated when that particular bit/signal is LOW 1: Active HIGH. An interrupt will be generated when that particular bit/signal is HIGH
`dma_config`	`0x90`	`32`	`RW`	`0x0`	Control/Status Word Register
`imgcfg_fifo_status`	`0x94`	`32`	`RO`	`0x200`	Control/Status Word Register