misci

         Provides a low-latency, low-performance, and simple way to read specific handshaking signals driven from the FPGA fabric.

Module Instance	Base Address	Register Address
`i_fpga_mgr_fpgamgrregs`	`0xFFD03000`	`0xFFD03018`

Offset: 0x18

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`														`bootFPGArdy` `RO 0x0`	`bootFPGAfail` `RO 0x0`

misci Fields

Bit	Name	Description	Access	Reset
1	`bootFPGArdy`	The value of the f2s_boot_from_fpga_ready signal from the FPGA fabric. If the FPGA is not in User Mode, the value of this field is undefined. 1 = FPGA fabric is ready to accept AXI master requests from the HPS2FPGA bridge. 0 = FPGA fabric is not ready (probably still processing a reset).	`RO`	`0x0`
0	`bootFPGAfail`	The value of the f2s_boot_from_fpga_on_failure signal from the FPGA fabric. If the FPGA is not in User Mode, the value of this field is undefined. 1 = Boot ROM will boot from FPGA if boot from normal boot device fails. 0 = Boot ROM will not boot from FPGA if boot from normal boot device fails.	`RO`	`0x0`

Bit

Name

Description

Access

Reset

bootFPGArdy

The value of the f2s_boot_from_fpga_ready signal from the FPGA fabric. If the FPGA is not in User Mode, the value of this field is undefined.
  1 = FPGA fabric is ready to accept AXI master requests from the HPS2FPGA bridge.
  0 = FPGA fabric is not ready (probably still processing a reset).

RO

0x0

bootFPGAfail

The value of the f2s_boot_from_fpga_on_failure signal from the FPGA fabric. If the FPGA is not in User Mode, the value of this field is undefined.
  1 = Boot ROM will boot from FPGA if boot from normal boot device fails.
  0 = Boot ROM will not boot from FPGA if boot from normal boot device fails.

RO

0x0