jtag_config
This register is used to configure the JTAG master interface.
It is recommended that software write this register before initiating a transfer.
If the software writes to this register while an active session is in progress (as indicated by jtag_status.SessionStatus), the expected behavior is "undefined".
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_fpga_mgr_fpgamgrregs | 0xFFD03000 | 0xFFD03050 |
Offset: 0x50
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
txSize RW 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
tckRatio RW 0x14 |
Reserved |
trstEn RW 0x0 |
Reserved |
loopBackEn RW 0x0 |
jtagPortEn RW 0x0 |
JtagHostEn RW 0x0 |
|||||||||
jtag_config Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:16 | txSize | Defines the number of bits to be transmitted. Once the software kicks of the transfer via Start_Transfer bits, the hardware will stop the transfer, when either of the below conditions are reached. a) Completed a transfer of programmed Number of TX Bits +1. b) TxFifo became empty (under-run of TxFifo). c) A Stop Transfer request received from software. So for a successful transfer of fixed number of bits, software has to make sure continuous flow of data. The exact number of bits to be transferred in the current session is 1+ the value in this register field. For example 0 -> 1 bit to be transmitted once start session is triggered. 1-> 2 bits to be transmitted.once start session is triggered. |
RW | 0x0 | ||||||
| 15:8 | tckRatio | Ratio of TCK division. The FPGA manager clock is 100MHz. value of 4 provides a 25MHz TCK value of 20 (0x14) provides a 5MHz TCK. Maximum supported TCK frequency is 25MHz. So writing a value less than 4 to this field will cause unexpected behavior. |
RW | 0x14 | ||||||
| 4 | trstEn | Set this bit and then writing at least 1 data in jtag_data_w will cause a JTAG reset to happen. Please note that writing TRSTEN while a data transmission is undergoing could cause undesired effects, so it is recommended that software poll the SESSIONSTATUS bit to make sure there is no existing transfers before writing TRSTEN. Software should manually write 0 to this bit after the completion of the reset and after the SESSIONSTATUS is inactive. |
RW | 0x0 | ||||||
| 2 | loopBackEn | Enables the internal loopback mode. A typical scenario will be to set JtagHostEn=0, JtagPortEn=0, and then initiate transmits by software writes to TXFifo. All transfers should receive back on RxFifo. Also this should not affect anything external, since the Jtag ports will be gated off.
|
RW | 0x0 | ||||||
| 1 | jtagPortEn | This bit field gates off TDI/TMS/TCK driven to the FPGA CSS interface. This allows the software to take over JTAG but keep them tied low. If this bit is 0 the internal core logic will still be active and all the status will be updated as in regular operation.
|
RW | 0x0 | ||||||
| 0 | JtagHostEn | This bit field drives the enable signal to the FPGA CSS. Please note that this enable should be driven long before you start any JTAG transactions.
|
RW | 0x0 |