jtag_data_r

         A read to this field initiates a read to the RxFifo. Please note that the read always returns a 16 bit value. If the received number of bits are not aligned with 16, lower most n bits should be ignored by software. For example in the case of 6 bits received, rdata[15:10] will contain received bits and rdata[9:0] should be ignored. A read of the fifo while empty is not defined.

Both the fifos are 8 words deep. So you can have up to 128 bits buffered in the FIFOs. If you have more than 128 bits to be transferred, and want continuous transfer software should make sure proper data flow to avoid a Tx-Fifo under-run or Rx-Fifo over-run. A Rx-Fifo over-run will cause silent data loss, and a Tx-Fifo under-run will stop the transfer, and will stop the TCK toggles, till another transfer is initiated by software.
At 5MHz jtag clock 16x100/5 = 320 cycles of FPGA manager clock to transfer 1 word of data
At 25Mhz jtag clock 16x100/25 = 64 cycles of FPGA manager clock to transfer 1 word of data.