dma_config

         Consist of control bit and status information.

Module Instance	Base Address	Register Address
`i_fpga_mgr_fpgamgrregs`	`0xFFD03000`	`0xFFD03090`

Offset: 0x90

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`															`clearFifo` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`dmareq_enable` `0x0`	`dmareq_level` `0x0`

dma_config Fields

Bit

Name

Description

Access

Reset

clearFifo

A write 1 to this bit field will empty the TxFifo. A read will always return 0.

RW

0x0

dmareq_enable

Writing 1 will enable DMA request handshake from FPGA manager.
Writing 0 will disable DMA request handshake from FPGA manager.

Value	Description
0	DMA request handshake disable.
1	DMA request handshake enable

RW

0x0

7:0

dmareq_level

DMA request threshold level

RW

0x0