intr_mask

         Mask for interrupts. A value of 1 in a particular bit will cause the specific interrupt to be masked.

Module Instance	Base Address	Register Address
`i_fpga_mgr_fpgamgrregs`	`0xFFD03000`	`0xFFD03088`

Offset: 0x88

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`		`emr` `RW 0x1`	`jtagm` `RW 0x1`	`Reserved`		`imgcfg_FifoFull` `RW 0x1`	`imgcfg_FifoEmpty` `RW 0x1`	`Reserved`					`f2s_msel2` `RW 0x1`	`f2s_msel1` `RW 0x1`	`f2s_msel0` `RW 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`		`f2s_nceo_oe` `RW 0x1`	`f2s_nconfig_pin` `RW 0x1`	`f2s_pr_error` `RW 0x1`	`f2s_pr_done` `RW 0x1`	`f2s_pr_ready` `RW 0x1`	`f2s_cvp_conf_done` `RW 0x1`	`f2s_condone_oe` `RW 0x1`	`f2s_condone_pin` `RW 0x1`	`f2s_nstatus_oe` `RW 0x1`	`f2s_nstatus_pin` `RW 0x1`	`f2s_initdone_oe` `RW 0x1`	`f2s_usermode` `RW 0x1`	`f2s_early_usermode` `RW 0x1`	`f2s_crc_error` `RW 0x1`

intr_mask Fields

Bit	Name	Description	Access	Reset
29	`emr`	EMR valid bit	`RW`	`0x1`
28	`jtagm`	JTAG Master Session Status	`RW`	`0x1`
25	`imgcfg_FifoFull`	FIfoFull Status of FPGA image configuration FIFO	`RW`	`0x1`
24	`imgcfg_FifoEmpty`	FIfoEmpty Status of FPGA image configuration FIFO	`RW`	`0x1`
18	`f2s_msel2`		`RW`	`0x1`
17	`f2s_msel1`		`RW`	`0x1`
16	`f2s_msel0`		`RW`	`0x1`
13	`f2s_nceo_oe`		`RW`	`0x1`
12	`f2s_nconfig_pin`		`RW`	`0x1`
11	`f2s_pr_error`		`RW`	`0x1`
10	`f2s_pr_done`		`RW`	`0x1`
9	`f2s_pr_ready`		`RW`	`0x1`
8	`f2s_cvp_conf_done`		`RW`	`0x1`
7	`f2s_condone_oe`		`RW`	`0x1`
6	`f2s_condone_pin`		`RW`	`0x1`
5	`f2s_nstatus_oe`		`RW`	`0x1`
4	`f2s_nstatus_pin`		`RW`	`0x1`
3	`f2s_initdone_oe`		`RW`	`0x1`
2	`f2s_usermode`		`RW`	`0x1`
1	`f2s_early_usermode`		`RW`	`0x1`
0	`f2s_crc_error`		`RW`	`0x1`