imgcfg_stat

         This is the unmasked status.
Value of corresponding inputs from CSS or PINs, without considering the intr_mask or intr_polarity.

Module Instance	Base Address	Register Address
`i_fpga_mgr_fpgamgrregs`	`0xFFD03000`	`0xFFD03080`

Offset: 0x80

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`		`emr` `RO 0x0`	`jtagm` `RO 0x0`	`Reserved`		`imgcfg_FifoFull` `RO 0x0`	`imgcfg_FifoEmpty` `RO 0x1`	`Reserved`					`f2s_msel2` `RO 0x0`	`f2s_msel1` `RO 0x0`	`f2s_msel0` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`		`f2s_nceo_oe` `RO 0x0`	`f2s_nconfig_pin` `RO 0x0`	`f2s_pr_error` `RO 0x0`	`f2s_pr_done` `RO 0x0`	`f2s_pr_ready` `RO 0x0`	`f2s_cvp_conf_done` `RO 0x0`	`f2s_condone_oe` `RO 0x0`	`f2s_condone_pin` `RO 0x0`	`f2s_nstatus_oe` `RO 0x0`	`f2s_nstatus_pin` `RO 0x0`	`f2s_initdone_oe` `RO 0x0`	`f2s_usermode` `RO 0x0`	`f2s_early_usermode` `RO 0x0`	`f2s_crc_error` `RO 0x0`

imgcfg_stat Fields

Bit	Name	Description	Access	Reset
29	`emr`	EMR valid bit	`RO`	`0x0`
28	`jtagm`	JTAG Master Session Status	`RO`	`0x0`
25	`imgcfg_FifoFull`	FIfoFull Status of FPGA image configuration FIFO	`RO`	`0x0`
24	`imgcfg_FifoEmpty`	FIfoEmpty Status of FPGA image configuration FIFO	`RO`	`0x1`
18	`f2s_msel2`	This read-only field allows software to observe the MSEL inputs from the device pins. The MSEL pins define the FPGA configuration mode. Please refer to CSS functional specifications for the exact definitions of MSEL encoding. In Arria 10 only 3 of these are used. Other bits will always read 0.	`RO`	`0x0`
17	`f2s_msel1`	This read-only field allows software to observe the MSEL inputs from the device pins. The MSEL pins define the FPGA configuration mode. Please refer to CSS functional specifications for the exact definitions of MSEL encoding. In Arria 10 only 3 of these are used. Other bits will always read 0.	`RO`	`0x0`
16	`f2s_msel0`	This read-only field allows software to observe the MSEL inputs from the device pins. The MSEL pins define the FPGA configuration mode. Please refer to CSS functional specifications for the exact definitions of MSEL encoding. In Arria 10 only 3 of these are used. Other bits will always read 0.	`RO`	`0x0`
13	`f2s_nceo_oe`	Chip select output enable driven from Control Subsystem.	`RO`	`0x0`
12	`f2s_nconfig_pin`	The value of this pin is used for monitoring purposes only in the FPGA manager.	`RO`	`0x0`
11	`f2s_pr_error`	Partial reconfiguration error	`RO`	`0x0`
10	`f2s_pr_done`	Partial reconfiguration done status	`RO`	`0x0`
9	`f2s_pr_ready`	Partial reconfiguration ready	`RO`	`0x0`
8	`f2s_cvp_conf_done`	Configuration via PCIe done indicator.	`RO`	`0x0`
7	`f2s_condone_oe`	This is the driven output enable of condone from the Control Subsystem (CSS). This signal can be used by software to determine the true status of the CSS.	`RO`	`0x0`
6	`f2s_condone_pin`	Sampled pin value for monitoring purposes only in FPGA manager. Please note that this value can be overriden by external devices.	`RO`	`0x0`
5	`f2s_nstatus_oe`	This is the driven output enable of nstatus from the Control Subsystem (CSS). This signal can be used by software to determine true status of the CSS.	`RO`	`0x0`
4	`f2s_nstatus_pin`	This status bit holds the signal value of nstatus which the Control Subsystem (CSS) sees when override is enabled, irrespective of what the pin value is. When this signal is 1, it doesn’t affect the pin value. When this signal is 1, it pulls down the pin value (irrespective override enable).	`RO`	`0x0`
3	`f2s_initdone_oe`	This bit indicates the true status of the Control Subsystem.	`RO`	`0x0`
2	`f2s_usermode`	User mode status. Asserted only when FPGA has finally entered user mode. The FPGA manager receives this signal after a glitch filter external to FPGA manager. This glitch filtered signal is named fpga_config_complete.	`RO`	`0x0`
1	`f2s_early_usermode`	Status of early user mode signal from the Control Subsystem (CSS). Used by software to determine status of when HPS is configuring the shared IOs via sending POF to CSS.	`RO`	`0x0`
0	`f2s_crc_error`	CRC error indicator.	`RO`	`0x0`