imgcfg_ctrl_02

         Allows HPS to control FPGA configuration.

The NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields drive signals to the FPGA Control Block that are logically ORed into their respective pins. These signals are always driven independent of the value of EN. The polarity of the NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields is inverted relative to their associated pins.

The MSEL (external pins), CDRATIO and CFGWDTH signals determine the mode of operation for Normal Configuration. For Partial Reconfiguration, CDRATIO is used to set the appropriate clock to data ratio, and CFGWDTH should always be set to 16-bit Passive Parallel.

AXICFGEN is used to enable transfer of configuration data by enabling or disabling DCLK during data transfers.

Module Instance	Base Address	Register Address
`i_fpga_mgr_fpgamgrregs`	`0xFFD03000`	`0xFFD03078`

Offset: 0x78

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`							`cfgwidth` `RW 0x0`	`Reserved`						`cdratio` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`en_cfg_data` `RW 0x0`	`Reserved`							`en_cfg_ctrl` `0x0`

imgcfg_ctrl_02 Fields

Bit

Name

Description

Access

Reset

cfgwidth

This field determines the Configuration Passive Parallel data bus width when HPS configures the FPGA.   Only 32-bit Passive Parallel or 16-bit Passive Parallel are supported.

When HPS does Normal Configuration, configuration should use 32-bit Passive Parallel Mode.   The external pins MSEL must be set appropriately for the configuration selected.

For Partial Reconfiguration, 16-bit Passive Parallel must be used.

Value	Description
0	PPx16
1	PPx32

RW

0x0

17:16

cdratio

This field controls the Clock to Data Ratio (CDRATIO) for Normal Configuration and Partial Reconfiguration data transfer from the AXI Slave to the FPGA.

For Normal Configuration, the value in this field must be set to be consistent to the implied CD ratio of the MSEL setting.

For Partial Reconfiguration, the value in this field must be set to the same clock to data ratio in the options bits in the Normal Configuration file.

Value	Description
0	x1
1	x2
2	x4
3	x8

RW

0x0

en_cfg_data

this is an unused software bit

RW

0x0

en_cfg_ctrl

If this bit is not enabled, the s2f_dclk as well as s2f_data will be always driven 0.
This is to provide a mechanism by which HPS can take over the DCLK/DATA by first setting the nenable_dclk even while s2f_dclk and s2f_data from HPS is silent.

RW

0x0