i2c_emac Address Map

Module Instance	Base Address	End Address
`i_i2c_emac_0_i2c`	`0xFFC02400`	`0xFFC024FF`
`i_i2c_emac_1_i2c`	`0xFFC02500`	`0xFFC025FF`
`i_i2c_emac_2_i2c`	`0xFFC02600`	`0xFFC026FF`

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Register	Offset	Width	Access	Reset Value	Description
`ic_con`	`0x0`	`32`	`RW`	`0x7D`	Name: I2C Control Register Size: 10 bits Address Offset: 0x00 Read/Write Access: If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0, all bits are Read/Write. If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
`ic_tar`	`0x4`	`32`	`RW`	`0x1055`	Name: I2C Target Address Register Size: 12 bits or 13 bits; 13 bits only when I2C_DYNAMIC_TAR_UPDATE = 1 Address Offset: 0x04 Read/Write Access: Read/Write If the configuration parameter I2C_DYNAMIC_TAR_UPDATE is set to 'No' (0), this register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. However, if I2C_DYNAMIC_TAR_UPDATE = 1, then the register becomes 13 bits wide. All bits can be dynamically updated as long as any set of the following conditions are true: - DW_apb_i2c is NOT enabled (IC_ENABLE[0] is set to 0); or - DW_apb_i2c is enabled (IC_ENABLE[0]=1); AND DW_apb_i2c is NOT engaged in any Master (tx, rx) operation (IC_STATUS[5]=0); AND DW_apb_i2c is enabled to operate in Master mode (IC_CON[0]=1); AND there are NO entries in the TX FIFO (IC_STATUS[2]=1)
`ic_sar`	`0x8`	`32`	`RW`	`0x55`	Name: I2C Slave Address Register Size: 10 bits Address Offset: 0x08 Read/Write Access: Read/Write
`ic_data_cmd`	`0x10`	`32`	`RW`	`0x0`	Name: I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO Size: When IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 11 bits (writes), 8 bits (read) When IC_EMPTYFIFO_HOLD_MASTER_EN=0 - 9 bits (writes), 8 bits (read) Address Offset: 0x10 Read/Write Access: Read/Write NOTE: With nine bits required for writes, the DW_apb_i2c requires 16-bit data on the APB bus transfers when writing into the transmit FIFO. Eight-bit transfers remain for reads from the receive FIFO.
`ic_ss_scl_hcnt`	`0x14`	`32`	`RW`	`0x190`	Name: Standard Speed I2C Clock SCL High Count Register Size: 16 bits Address Offset: 0x14 Read/Write Access: Read/Write
`ic_ss_scl_lcnt`	`0x18`	`32`	`RW`	`0x1D6`	Name: Standard Speed I2C Clock SCL Low Count Register Size: 16 bits Address Offset: 0x18 Read/Write Access: Read/Write
`ic_fs_scl_hcnt`	`0x1C`	`32`	`RW`	`0x3C`	Name: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register Size: 16 bits Address Offset: 0x1c Read/Write Access: Read/Write
`ic_fs_scl_lcnt`	`0x20`	`32`	`RW`	`0x82`	Name: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register Size: 16 bits Address Offset: 0x20 Read/Write Access: Read/Write
`ic_intr_stat`	`0x2C`	`32`	`RO`	`0x0`	Name: I2C Interrupt Status Register Size: 14 bits Address Offset: 0x2C Read/Write Access: Read Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.
`ic_intr_mask`	`0x30`	`32`	`RW`	`0x8FF`	Name: I2C Interrupt Mask Register Size: 14 bits Address Offset: 0x30 Read/Write Access: Read/Write However, if configuration parameter IC_SLV_RESTART_DET = 0, bit 13 is read only; if configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0 or IC_EMPTYFIFO_HOLD_MASTER_EN = 0, bit 14 is read only. These bits mask their corresponding interrupt status bits. They are active high; a value of 0 prevents a bit from generating an interrupt.
`ic_raw_intr_stat`	`0x34`	`32`	`RO`	`0x0`	Name: I2C Raw Interrupt Status Register Size: 14 bits Address Offset: 0x34 Read/Write Access: Read Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.
`ic_rx_tl`	`0x38`	`32`	`RW`	`0x0`	Name: I2C Receive FIFO Threshold Register Size: 8bits Address Offset: 0x38 Read/Write Access: Read/Write
`ic_tx_tl`	`0x3C`	`32`	`RW`	`0x0`	Name: I2C Transmit FIFO Threshold Register Size: 8 bits Address Offset: 0x3c Read/Write Access: Read/Write
`ic_clr_intr`	`0x40`	`32`	`RO`	`0x0`	Name: Clear Combined and Individual Interrupt Register Size: 1 bit Address Offset: 0x40 Read/Write Access: Read
`ic_clr_rx_under`	`0x44`	`32`	`RO`	`0x0`	Name: Clear RX_UNDER Interrupt Register Size: 1 bit Address Offset: 0x44 Read/Write Access: Read
`ic_clr_rx_over`	`0x48`	`32`	`RO`	`0x0`	Name: Clear RX_OVER Interrupt Register Size: 1 bit Address Offset: 0x48 Read/Write Access: Read
`ic_clr_tx_over`	`0x4C`	`32`	`RO`	`0x0`	Name: Clear TX_OVER Interrupt Register Size: 1 bit Address Offset: 0x4c Read/Write Access: Read
`ic_clr_rd_req`	`0x50`	`32`	`RO`	`0x0`	Name: Clear RD_REQ Interrupt Register Size: 1 bit Address Offset: 0x50 Read/Write Access: Read
`ic_clr_tx_abrt`	`0x54`	`32`	`RO`	`0x0`	Name: Clear TX_ABRT Interrupt Register Size: 1 bit Address Offset: 0x54 Read/Write Access: Read
`ic_clr_rx_done`	`0x58`	`32`	`RO`	`0x0`	Name: Clear RX_DONE Interrupt Register Size: 1 bit Address Offset: 0x58 Read/Write Access: Read
`ic_clr_activity`	`0x5C`	`32`	`RO`	`0x0`	Name: Clear ACTIVITY Interrupt Register Size: 1 bit Address Offset: 0x5c Read/Write Access: Read
`ic_clr_stop_det`	`0x60`	`32`	`RO`	`0x0`	Name: Clear STOP_DET Interrupt Register Size: 1 bit Address Offset: 0x60 Read/Write Access: Read
`ic_clr_start_det`	`0x64`	`32`	`RO`	`0x0`	Name: Clear START_DET Interrupt Register Size: 1 bit Address Offset: 0x64 Read/Write Access: Read
`ic_clr_gen_call`	`0x68`	`32`	`RO`	`0x0`	Name: Clear GEN_CALL Interrupt Register Size: 1 bit Address Offset: 0x68 Read/Write Access: Read
`ic_enable`	`0x6C`	`32`	`RW`	`0x0`	Name: I2C Enable Register Size: 2 bits Address Offset: 0x6c Read/Write Access: Read/Write
`ic_status`	`0x70`	`32`	`RO`	`0x6`	Name: I2C Status Register Size: 7 bits Address Offset: 0x70 Read/Write Access: Read This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 4 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0
`ic_txflr`	`0x74`	`32`	`RO`	`0x0`	Name: I2C Transmit FIFO Level Register Size: TX_ABW + 1 Address Offset: 0x74 Read/Write Access: Read This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
`ic_rxflr`	`0x78`	`32`	`RO`	`0x0`	Name: I2C Receive FIFO Level Register Size: RX_ABW + 1 Address Offset: 0x78 Read/Write Access: Read This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
`ic_sda_hold`	`0x7C`	`32`	`RW`	`0x1`	Name: I2C SDA Hold Time Length Register Size: 24 bits Address Offset: 0x7c Read/Write Access: Read/Write The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. The values in this register are in units of ic_clk period. This register controls the amount of time delay. The relevant I2C requirement is thd:DAT as detailed in the I2C Bus Specification.
`ic_tx_abrt_source`	`0x80`	`32`	`RO`	`0x0`	Name: I2C Transmit Abort Source Register Size: 32 bits Address Offset: 0x80 Read/Write Access: Read This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.
`ic_slv_data_nack_only`	`0x84`	`32`	`RW`	`0x0`	Name: Generate Slave Data NACK Register Size: 1 bit Address Offset: 0x84 Read/Write Access: Read/Write The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.
`ic_dma_cr`	`0x88`	`32`	`RW`	`0x0`	Name: DMA Control Register Size: 2 bits Address Offset: 0x88 Read/Write Access: Read/Write This register is only valid when DW_apb_i2c is configured with a set of DMA Controller interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation, this register does not exist and writing to the register’s address has no effect and reading from this register address will return zero. The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.
`ic_dma_tdlr`	`0x8C`	`32`	`RW`	`0x0`	Name: DMA Transmit Data Level Register Size: log2(IC_TX_BUFFER_DEPTH) bits Address Offset: 0x8c Read/Write Access: Read/Write This register is only valid when the DW_apb_i2c is configured with a set of DMA interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation, this register does not exist; writing to its address has no effect; reading from its address returns zero.
`ic_dma_rdlr`	`0x90`	`32`	`RW`	`0x0`	Name: I2C Receive Data Level Register Size: log2(IC_RX_BUFFER_DEPTH) bits Address Offset: 0x90 Read/Write Access: Read/Write This register is only valid when DW_apb_i2c is configured with a set of DMA interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation, this register does not exist; writing to its address has no effect; reading from its address returns zero.
`ic_sda_setup`	`0x94`	`32`	`RW`	`0x64`	Name: I2C SDA Setup Register Size: 8 bits Address Offset: 0x94 Read/Write Access: Read/Write This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL, relative to SDA changing, when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification.
`ic_ack_general_call`	`0x98`	`32`	`RW`	`0x1`	Name: I2C ACK General Call Register Size: 1 bit Address Offset: 0x98 Read/Write Access: Read/Write The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. Note :This register is applicable only when the DW_apb_i2c is in slave mode
`ic_enable_status`	`0x9C`	`32`	`RO`	`0x0`	Name: I2C Enable Status Register Size: 3 bits Address Offset: 0x9C Read/Write Access: Read The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note When IC_ENABLE[0] has been written with '0'a delay occurs for bit 0 to be read as '0' because disabling the DW_apb_i2c depends on I2C bus activities.
`ic_comp_param_1`	`0xF4`	`32`	`RO`	`0x3F3FEA`	Name: Component Parameter Register 1 Size: 32 bits Address Offset: 0xf4 Read/Write Access: Read Note This is a constant read-only register that contains encoded information about the component's parameter settings. The reset value depends on coreConsultant parameter(s).
`ic_comp_version`	`0xF8`	`32`	`RO`	`0x3132312A`	Name: I2C Component Version Register Size: 32 bits Address Offset: 0xf8 Read/Write Access: Read
`ic_comp_type`	`0xFC`	`32`	`RO`	`0x44570140`	Name: I2C Component Type Register Size: 32 bits Address Offset: 0xfc Read/Write Access: Read
`ic_fs_spklen`	`0xA0`	`32`	`RW`	`0x2`	Name: I2C SS, FS or FM+ spike suppression limit Size: 8 bits Address: 0xA0 Read/Write Access: Read/Write This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic w hen the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.
`ic_clr_restart_det`	`0xA8`	`32`	`RO`	`0x0`	Name: Clear RESTART_DET Interrupt Register Size: 1 bit Address Offset: 0xA8 Read/Write Access: Read