ic_data_cmd

         I2C Rx/Tx Data Buffer and Command Register;
      this is the register the CPU writes to when
      filling the TX FIFO and the CPU reads from when
      retrieving bytes from RX FIFO
Size: 
11 bits (writes), 8 bits (read)

Module Instance	Base Address	Register Address
`i_i2c_emac_0_i2c`	`0xFFC02400`	`0xFFC02410`
`i_i2c_emac_1_i2c`	`0xFFC02500`	`0xFFC02510`
`i_i2c_emac_2_i2c`	`0xFFC02600`	`0xFFC02610`

Offset: 0x10

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`					`restart` `WO 0x0`	`stop` `WO 0x0`	`cmd` `WO 0x0`	`dat` `RW 0x0`

ic_data_cmd Fields

Bit

Name

Description

Access

Reset

restart

This bit controls whether a RESTART is issued before the byte is sent or received.

1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is
sent/received (according to the value of CMD), regardless of whether or not the
transfer direction is changing from the previous command; if IC_RESTART_EN
is 0, a STOP followed by a START is issued instead.
0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is
changing from the previous command; if IC_RESTART_EN is 0, a STOP followed
by a START is issued instead.
Reset value: 0x0

WO

0x0

stop

This bit controls whether a STOP is issued after the byte is sent or received.

1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is
empty. If the Tx FIFO is not empty, the master immediately tries to start a new
transfer by issuing a START and arbitrating for the bus.
0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is
empty. If the Tx FIFO is not empty, the master continues the current transfer by
sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO
is empty, the master holds the SCL line low and stalls the bus until a new
command is available in the Tx FIFO.
Reset value: 0x0

WO

0x0

cmd

This bit controls whether a read or a write is performed.
This bit does not control the direction when the DW_apb_i2c
acts as a slave. It controls only the direction
when it acts as a master.
1 = Read
0 = Write
When a command is entered in the TX FIFO, this bit distinguishes the write and
read commands. In slave-receiver mode, this bit is a 'don't care' because writes to
this register are not required. In slave-transmitter mode, a '0' indicates that CPU
data is to be transmitted and as DAT or IC_DATA_CMD[7:0].
When programming this bit, you should remember the following: attempting to
perform a read operation after a General Call command has been sent results in a
TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11
(SPECIAL) in the IC_TAR register has been cleared.
If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT
interrupt occurs.
NOTE: It is possible that while attempting a master I2C read transfer on
the I2C, a RD_REQ interrupt may have occurred simultaneously due to a
remote I2C master addressing the I2C module. In this type of scenario,the I2C module
ignores the IC_DATA_CMD write, generates a TX_ABRT interrupt, and waits to
service the RD_REQ interrupt.
Reset value: 0x0

Value	Description
0x0	WR
0x1	RD

WO

0x0

7:0

dat

This register contains the data to be transmitted or received on the I2C bus.
If you are writing to this register and want to perform a read,
bits 7:0 (DAT) are ignored by the I2C moudle. However, when you read
this register, these bits return the value of data received on the
the I2C interface.
Reset value: 0x0

RW

0x0