ic_clr_intr

         Clear Combined and Individual Interrupt Register

Module Instance	Base Address	Register Address
`i_i2c_emac_0_i2c`	`0xFFC02400`	`0xFFC02440`
`i_i2c_emac_1_i2c`	`0xFFC02500`	`0xFFC02540`
`i_i2c_emac_2_i2c`	`0xFFC02600`	`0xFFC02640`

Offset: 0x40

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`clr_intr` `RO 0x0`

ic_clr_intr Fields

Bit	Name	Description	Access	Reset
0	`clr_intr`	Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0	`RO`	`0x0`

Bit

Name

Description

Access

Reset

clr_intr

Read this register to clear the combined interrupt,
all individual interrupts, and the IC_TX_ABRT_SOURCE register.
This bit does not clear hardware clearable interrupts but software
clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register
for an exception to clearing IC_TX_ABRT_SOURCE.
Reset value: 0x0

RO

0x0