ic_dma_cr
DMA Control Register
The register is used to enable the DMA Controller interface operation.
There is a separate bit for transmit and receive. This can be programmed
regardless of the state of IC_ENABLE.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_i2c_emac_0_i2c | 0xFFC02400 | 0xFFC02488 |
| i_i2c_emac_1_i2c | 0xFFC02500 | 0xFFC02588 |
| i_i2c_emac_2_i2c | 0xFFC02600 | 0xFFC02688 |
Offset: 0x88
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
rsvd_ic_dma_cr_31to2 RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
rsvd_ic_dma_cr_31to2 RO 0x0 |
tdmae RW 0x0 |
rdmae RW 0x0 |
|||||||||||||
ic_dma_cr Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:2 | rsvd_ic_dma_cr_31to2 | Reserved bits [31:1] - Read Only |
RO | 0x0 | ||||||
| 1 | tdmae | Transmit DMA Enable. //This bit enables/disables the transmit FIFO DMA channel. 0 = Transmit DMA disabled 1 = Transmit DMA enabled Reset value: 0x0
|
RW | 0x0 | ||||||
| 0 | rdmae | Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. 0 = Receive DMA disabled 1 = Receive DMA enabled Reset value: 0x0
|
RW | 0x0 |