ic_rx_tl

         I2C Receive FIFO Threshold Register

Module Instance	Base Address	Register Address
`i_i2c_emac_0_i2c`	`0xFFC02400`	`0xFFC02438`
`i_i2c_emac_1_i2c`	`0xFFC02500`	`0xFFC02538`
`i_i2c_emac_2_i2c`	`0xFFC02600`	`0xFFC02638`

Offset: 0x38

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`rx_tl` `RW 0x0`

ic_rx_tl Fields

Bit	Name	Description	Access	Reset
7:0	`rx_tl`	Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

7:0

rx_tl

Receive FIFO Threshold Level
Controls the level of entries (or above) that triggers
the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register).
The valid range is 0-255, with the additional restriction that
hardware does not allow this value to be set to a value larger
than the depth of the buffer. If an attempt is made to do that,
the actual value set will be the maximum depth of the buffer.
A value of 0 sets the threshold for 1 entry, and a value of 255
sets the threshold for 256 entries.

RW

0x0