ic_status
I2C Status Register
This is a read-only register used to indicate the current
transfer status and FIFO status. The status register may be
read at any time. None of the bits in this register request
an interrupt.
When the I2C is disabled by writing 0 in bit 0 of the
IC_ENABLE register:
- Bits 1 and 2 are set to 1
- Bits 3 and 4 are set to 0
When the master or slave state machines goes to idle
and ic_en=0:
- Bits 5 and 6 are set to 0
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_i2c_emac_0_i2c | 0xFFC02400 | 0xFFC02470 |
| i_i2c_emac_1_i2c | 0xFFC02500 | 0xFFC02570 |
| i_i2c_emac_2_i2c | 0xFFC02600 | 0xFFC02670 |
Offset: 0x70
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
slv_activity RO 0x0 |
mst_activity RO 0x0 |
rff RO 0x0 |
rfne RO 0x0 |
tfe RO 0x1 |
tfnf RO 0x1 |
activity RO 0x0 |
||||||||
ic_status Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 6 | slv_activity | Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Slave FSM is in IDLE state so the Slave part of I2C module is not Active 1: Slave FSM is not in IDLE state so the Slave part of the I2C module is Active Reset value: 0x0
|
RO | 0x0 | ||||||
| 5 | mst_activity | Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Master FSM is in IDLE state so the Master part of the I2C module is not Active 1: Master FSM is not in IDLE state so the Master part of the I2C module is Active Note IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0
|
RO | 0x0 | ||||||
| 4 | rff | Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0: Receive FIFO is not full 1: Receive FIFO is full Reset value: 0x0
|
RO | 0x0 | ||||||
| 3 | rfne | Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. 0: Receive FIFO is empty 1: Receive FIFO is not empty Reset value: 0x0
|
RO | 0x0 | ||||||
| 2 | tfe | Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0: Transmit FIFO is not empty 1: Transmit FIFO is empty Reset value: 0x1
|
RO | 0x1 | ||||||
| 1 | tfnf | Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0: Transmit FIFO is full 1: Transmit FIFO is not full Reset value: 0x1
|
RO | 0x1 | ||||||
| 0 | activity | I2C Activity Status. Reset value: 0x0 |
RO | 0x0 |