ic_intr_mask

         I2C Interrupt Mask Register

These bits mask their corresponding interrupt status bits.
They are active high; a value of 0 prevents a bit from
generating an interrupt.
Module Instance Base Address Register Address
i_i2c_emac_0_i2c 0xFFC02400 0xFFC02430
i_i2c_emac_1_i2c 0xFFC02500 0xFFC02530
i_i2c_emac_2_i2c 0xFFC02600 0xFFC02630

Offset: 0x30

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

m_master_on_hold

RW 0x0

m_restart_det

RW 0x0

m_gen_call

RW 0x1

m_start_det

RW 0x0

m_stop_det

RW 0x0

m_activity

RW 0x0

m_rx_done

RW 0x1

m_tx_abrt

RW 0x1

m_rd_req

RW 0x1

m_tx_empty

RW 0x1

m_tx_over

RW 0x1

m_rx_full

RW 0x1

m_rx_over

RW 0x1

m_rx_under

RW 0x1

ic_intr_mask Fields

Bit Name Description Access Reset
13 m_master_on_hold 
This bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.
Reset value: 0x0
 RW 0x0
12 m_restart_det 
This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.
Reset value: 0x0
 RW 0x0
11 m_gen_call 
This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.
Reset value: 0x1
 RW 0x1
10 m_start_det 
This bit masks the R_START_DET interrupt in IC_INTR_STAT register.
Reset value: 0x0
 RW 0x0
9 m_stop_det 
This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.
Reset value: 0x0
 RW 0x0
8 m_activity 
This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.
Reset value: 0x0
 RW 0x0
7 m_rx_done 
This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.
Reset value: 0x1
 RW 0x1
6 m_tx_abrt 
This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.
Reset value: 0x1
 RW 0x1
5 m_rd_req 
This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
Reset value: 0x1
 RW 0x1
4 m_tx_empty 
This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.
Reset value: 0x1
 RW 0x1
3 m_tx_over 
This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.
Reset value: 0x1
 RW 0x1
2 m_rx_full 
This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.
Reset value: 0x1
 RW 0x1
1 m_rx_over 
This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.
Reset value: 0x1
 RW 0x1
0 m_rx_under 
This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.
Reset value: 0x1
 RW 0x1