AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

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ID 848984
Date 4/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Preparing LiteRT Inference Model 3. Generating Nios® V Processor System 4. Generating Arm Processor System 5. Programming and Running 6. Appendix 7. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers
1. Overview x
1.1. Requirements
2. Preparing LiteRT Inference Model x
2.1. Defining the Problem 2.2. Gathering and Preparing Sample Data 2.3. Building TensorFlow Model 2.4. Preparing the LiteRT Model 2.5. Preparing Binaries for C/C++
2.2. Gathering and Preparing Sample Data x
2.2.1. Preparing Dataset 2.2.2. Preprocessing Dataset
2.3. Building TensorFlow Model x
2.3.1. Constructing Model Architecture 2.3.2. Configuring Model 2.3.3. Training Model 2.3.4. Evaluating the Model 2.3.5. Saving and Loading Model
2.4. Preparing the LiteRT Model x
2.4.1. Converting into LiteRT Model 2.4.2. Saving the LiteRT Model 2.4.3. Analyzing the LiteRT Model 2.4.4. Loading a LiteRT Interpreter 2.4.5. Evaluating the LiteRT Model
2.5. Preparing Binaries for C/C++ x
2.5.1. Converting LiteRT to a C Array 2.5.2. Preparing a Header File for LiteRT C Array 2.5.3. Preparing Supporting Header File for LiteRT C Array 2.5.4. Preparing Main Function to Run TinyML 2.5.5. Converting MNIST Sample into C Array
3. Generating Nios® V Processor System x
3.1. Building Hardware Design in Platform Designer 3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs
3.2. Building Software Design with Ashling* RiscFree* IDE for Altera® FPGAs x
3.2.1. Creating a Board Support Package 3.2.2. Building LiteRT for Microcontroller Static Library 3.2.3. Creating an Application Project File 3.2.4. Building the LiteRT TinyML Application
4. Generating Arm Processor System x
4.1. GHRD Hardware Design 4.2. Building the Software Design
4.2. Building the Software Design x
4.2.1. Arm-Trusted-Firmware 4.2.2. Building LiteRT for Microcontrollers Static Library 4.2.3. Zephyr OS Environment Setup 4.2.4. Building the LiteRT TinyML Application
4.2.1. Arm-Trusted-Firmware x
4.2.1.1. Booting from QSPI Flash 4.2.1.2. Running through Ashling* RiscFree* IDE for Altera® FPGAs Debugger
5. Programming and Running x
5.1. Nios® V Processor System 5.2. Arm HPS Processor System
5.2. Arm HPS Processor System x
5.2.1. Booting from QSPI 5.2.2. Booting via the Debugger
6. Appendix x
6.1. main.cc for Nios V Processor 6.2. main.cc for Arm HPS Processor
1. Overview
2. Preparing LiteRT Inference Model
3. Generating Nios® V Processor System
4. Generating Arm Processor System
5. Programming and Running
6. Appendix
7. Document Revision History for the AN 1011: TinyML Applications in Altera FPGAs Using LiteRT for Microcontrollers

4.2.1.2. Running through Ashling* RiscFree* IDE for Altera® FPGAs Debugger

You can customize the ATF BL2 source code to generate a custom bl2.bin file that allows you to download the SSBL (bl31.bin) and the application manually via the Ashling RiscFree debugger tool

Follow these steps:

  1. Download the ATF source code.
    $ cd $TOP_FOLDER
$ git clone -b socfpga_v2.11.0 https://github.com/altera-opensource/arm-trusted-firmware atf_tinyml
  2. Customize the ATF source code.

    BL2 must be customized in a way that allows the developer to debug the application or use the debugger tools to manually download the SSBL and the application binary files. Without this customization, you can generate the default BL2 version which expects the BL31 and the application to stored in QSPI flash (as shown in Booting from QSPI Flash).

    To generate a BL2 version that can be debugged, follow the steps below:
    1. Navigate to bl2_plat_setup.c file
      $ cd $TOP_FOLDER/atf_tinyml/plat/intel/soc/agilex5/
    2. Before the end of switch (boot_source) function, add the following codes:
      …
	NOTICE("%s, %s: BL2: Dummy BP for loading next images \n", __DATE__, __TIME__);
	mmio_write_32(0x10D12224, BIT(1));
	while (mmio_read_32(0x10D12224) != 0);
…
    3. Save the bl2_plat_setup.c file.
    4. Compile the ATF to generate Bl2 and BL31 binary files using the command below.
      $ cd $TOP_FOLDER/atf_tinyml
$ ARCH=arm64 CROSS_COMPILE=aarch64-none-linux-gnu- make -j$(nproc) 
PLAT=agilex5 bl2 bl31 SOCFPGA_BOOT_SOURCE_QSPI=1 DEBUG=1 LOG_LEVEL=50 
PRELOADED_BL33_BASE=0x80100000

      Where:

      DEBUG=1 isto enable the debug build.

      LOG_LEVEL=50 is to print some useful debug messages.

After that, you can navigate the build directory to find the required files, as below: 
$ cd $TOP_FOLDER/atf_tinyml/build/agilex5/debug/

The above flow generates the required BL2 and BL31 images. These files are used for debug purposes; the BL2 is loaded once the HPS .rbf file is loaded into the board, and BL31 is loaded into the board via Ashling RiscFree debugger tool.

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